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Searched refs:cached (Results 1 – 11 of 11) sorted by relevance

/u-boot/doc/
A DREADME.mpc85xx-spin-table3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
A DREADME.fuse59 This is useful to change the behaviors linked to some cached fuse values,
A DREADME.POST537 - write the negative pattern to a cached area
547 - write the zero pattern to a cached area
560 - write the zero pattern to a cached area
573 - write the negative pattern to a cached area
/u-boot/drivers/smem/
A Dmsm_smem.c349 void *cached; in qcom_smem_alloc_private() local
353 cached = phdr_to_last_cached_entry(phdr); in qcom_smem_alloc_private()
371 if ((void *)hdr + alloc_size >= cached) { in qcom_smem_alloc_private()
/u-boot/doc/board/sipeed/
A Dmaix.rst646 0x40000000 0x400000 sram0 (non-cached)
647 0x40400000 0x200000 sram1 (non-cached)
648 0x40600000 0x200000 airam (non-cached)
682 0x80000000 0x400000 sram0 (cached)
683 0x80400000 0x200000 sram1 (cached)
684 0x80600000 0x200000 airam (cached)
/u-boot/doc/arch/
A Dnios2.rst94 should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx
/u-boot/doc/device-tree-bindings/reserved-memory/
A Dreserved-memory.txt64 system can use that region to store volatile or cached data that
/u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/
A Dfsp-m.txt20 - fspm,training-delay: Time taken to train DDR memory if there is no cached MRC
/u-boot/arch/x86/
A DKconfig514 Enable this feature to cause MRC data to be cached in NV storage
553 Sets the size of the cached area for the memory reference code.
556 of cached space.
/u-boot/drivers/video/
A DKconfig50 allows the frame buffer to be kept in cached memory (allocated by
/u-boot/
A DREADME2410 Size of non-cached memory area. This area of memory will be
2426 Non-cached memory is only supported on 32-bit ARM at present.

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