Searched refs:cacheline (Results 1 – 6 of 6) sorted by relevance
| /u-boot/drivers/net/fsl-mc/dpio/ |
| A D | qbman_portal.h | 128 const uint32_t *cacheline) in qb_attr_code_decode() argument
130 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
136 uint32_t *cacheline, uint32_t val) in qb_attr_code_encode() argument
138 cacheline[code->word] = in qb_attr_code_encode()
139 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
144 uint64_t *cacheline, uint64_t val) in qb_attr_code_encode_64() argument
146 cacheline[code->word / 2] = val; in qb_attr_code_encode_64()
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| /u-boot/drivers/smem/ |
| A D | msm_smem.c | 157 __le32 cacheline; member
270 size_t cacheline[SMEM_HOST_COUNT]; member
286 size_t cacheline) in phdr_to_first_cached_entry() argument
318 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
322 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
497 size_t cacheline, in qcom_smem_get_private() argument
523 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
538 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
573 cacheln = __smem->cacheline[host]; in qcom_smem_get()
727 smem->global_cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_set_global_partition()
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| /u-boot/doc/ |
| A D | README.fsl-ddr | 70 # cacheline interleaving
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
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| /u-boot/include/configs/ |
| A D | T4240RDB.h | 603 #define CTRL_INTLV_PREFERED cacheline
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| A D | T208xRDB.h | 142 #define CTRL_INTLV_PREFERED cacheline
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| A D | T208xQDS.h | 160 #define CTRL_INTLV_PREFERED cacheline
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