Home
last modified time | relevance | path

Searched refs:ccm (Results 1 – 25 of 108) sorted by relevance

12345

/u-boot/arch/arm/mach-sunxi/
A Dclock_sun9i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
42 &ccm->ahb0_cfg); in clock_init_safe()
45 &ccm->ahb1_cfg); in clock_init_safe()
48 &ccm->ahb2_cfg); in clock_init_safe()
51 &ccm->apb0_cfg); in clock_init_safe()
55 &ccm->gtbus_cfg); in clock_init_safe()
58 &ccm->cci400_cfg); in clock_init_safe()
75 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
98 &ccm->pll1_c0_cfg); in clock_set_pll1()
124 &ccm->pll2_c1_cfg); in clock_set_pll2()
[all …]
A Dclock_sun8i_a83t.c22 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
28 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
32 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
54 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
61 &ccm->apb2_div); in clock_init_uart()
64 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
69 setbits_le32(&ccm->apb2_reset_cfg, in clock_init_uart()
86 &ccm->cpu_axi_cfg); in clock_set_pll1()
91 &ccm->pll1_c0_cfg); in clock_set_pll1()
96 &ccm->pll1_c1_cfg); in clock_set_pll1()
[all …]
A Dclock_sun6i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
68 struct sunxi_ccm_reg * const ccm = in clock_init_sec() local
73 setbits_le32(&ccm->ccu_sec_switch, in clock_init_sec()
87 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
94 &ccm->apb2_div); in clock_init_uart()
97 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
131 &ccm->cpu_axi_cfg); in clock_set_pll1()
146 &ccm->cpu_axi_cfg); in clock_set_pll1()
168 &ccm->pll3_cfg); in clock_set_pll3()
180 &ccm->pll3_cfg); in clock_set_pll3_factors()
[all …]
A Dclock_sun50i_h6.c10 struct sunxi_ccm_reg *const ccm = in clock_init_safe() local
40 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
47 &ccm->apb2_cfg); in clock_init_uart()
50 setbits_le32(&ccm->uart_gate_reset, in clock_init_uart()
61 struct sunxi_ccm_reg * const ccm = in clock_set_pll1() local
69 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
72 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
83 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
86 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
92 struct sunxi_ccm_reg *const ccm = in clock_get_pll6() local
[all …]
A Dclock_sun4i.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
50 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
60 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
66 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
71 setbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
74 clrbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
158 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
[all …]
A Dclock.c42 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
57 setbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
59 setbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
62 clrbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
64 clrbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
/u-boot/board/tbs/tbs2910/
A Dtbs2910.c104 reg = readl(&ccm->analog_pll_video); in setup_display()
106 writel(reg, &ccm->analog_pll_video); in setup_display()
112 writel(reg, &ccm->analog_pll_video); in setup_display()
118 writel(reg, &ccm->analog_pll_video); in setup_display()
126 reg = readl(&ccm->analog_pll_video); in setup_display()
132 reg = readl(&ccm->CCGR3); in setup_display()
134 writel(reg, &ccm->CCGR3); in setup_display()
137 reg = readl(&ccm->chsccdr); in setup_display()
144 writel(reg, &ccm->chsccdr); in setup_display()
147 reg = readl(&ccm->CCGR3); in setup_display()
[all …]
/u-boot/arch/arm/cpu/arm926ejs/mx25/
A Dgeneric.c62 return imx_decode_pll(readl(&ccm->mpctl), fref); in imx_get_mpllclk()
70 return imx_decode_pll(readl(&ccm->upctl), fref); in imx_get_upllclk()
76 ulong cctl = readl(&ccm->cctl); in imx_get_armclk()
92 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk()
114 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); in imx_get_perclk()
133 setbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()
135 clrbits_le32(&ccm->mcr, 1 << clk); in imx_set_perclk()
188 struct ccm_regs *ccm = in get_reset_cause() local
191 u32 cause = readl(&ccm->rcsr) & 0x0f; in get_reset_cause()
232 val = readl(&ccm->cgr0); in cpu_eth_init()
[all …]
/u-boot/arch/arm/cpu/arm1136/mx35/
A Dgeneric.c138 struct ccm_regs *ccm = in get_mcu_main_clk() local
148 struct ccm_regs *ccm = in get_ipg_clk() local
150 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
158 struct ccm_regs *ccm = in get_ipg_per_clk() local
160 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
179 struct ccm_regs *ccm = in imx_get_uartclk() local
197 struct ccm_regs *ccm = in mxc_get_main_clock() local
200 u32 reg = readl(&ccm->pdr0); in mxc_get_main_clock()
258 struct ccm_regs *ccm = in mxc_get_peri_clock() local
406 struct ccm_regs *ccm = in get_reset_cause() local
[all …]
/u-boot/board/ccv/xpress/
A Dspl.c82 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
84 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
85 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
86 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
87 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
88 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/u-boot/board/toradex/colibri_vf/
A Dcolibri_vf.c268 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
273 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
275 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
279 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
281 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
286 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
288 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
290 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
321 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
[all …]
/u-boot/board/barco/platinum/
A Dplatinum.h66 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
68 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
69 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
70 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
71 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
73 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
74 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/CarMediaLab/flea3/
A Dflea3.c138 struct ccm_regs *ccm = in board_early_init_f() local
146 writel(CCM_CCMR_CONFIG, &ccm->ccmr); in board_early_init_f()
148 writel(CCM_MPLL_532_HZ, &ccm->mpctl); in board_early_init_f()
149 writel(CCM_PPLL_300_HZ, &ccm->ppctl); in board_early_init_f()
152 writel(0x00001000, &ccm->pdr0); in board_early_init_f()
158 writel(readl(&ccm->cgr0) | in board_early_init_f()
162 &ccm->cgr0); in board_early_init_f()
164 writel(readl(&ccm->cgr1) | in board_early_init_f()
172 &ccm->cgr1); in board_early_init_f()
175 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); in board_early_init_f()
/u-boot/arch/arm/cpu/armv7/vf610/
A Dgeneric.c34 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
37 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
42 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
48 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
53 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
57 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
115 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
129 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
149 ccm_cscmr1 = readl(&ccm->cscmr1); in get_sdhc_clk()
153 ccm_cscdr2 = readl(&ccm->cscdr2); in get_sdhc_clk()
[all …]
/u-boot/board/phytec/pcm052/
A Dpcm052.c222 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
224 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
226 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
231 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
233 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
236 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
238 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
240 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
250 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
252 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dlitesom.c152 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
154 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
155 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
156 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
157 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
158 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
159 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
160 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
161 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
A Dopos6ul.c162 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
164 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
165 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
166 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
167 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
168 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
169 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
170 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
171 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dspeed.c33 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
47 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
51 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
60 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
64 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
74 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
78 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
106 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
119 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
133 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5445x_clocks() local
[all …]
/u-boot/board/freescale/vf610twr/
A Dvf610twr.c275 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
279 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
286 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
293 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
303 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
305 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/u-boot/board/bticino/mamoj/
A Dspl.c144 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
146 writel(0x00003f3f, &ccm->CCGR0); in ccgr_init()
147 writel(0x0030fc00, &ccm->CCGR1); in ccgr_init()
148 writel(0x000fc000, &ccm->CCGR2); in ccgr_init()
149 writel(0x3f300000, &ccm->CCGR3); in ccgr_init()
150 writel(0xff00f300, &ccm->CCGR4); in ccgr_init()
151 writel(0x0f0000c3, &ccm->CCGR5); in ccgr_init()
152 writel(0x000003cc, &ccm->CCGR6); in ccgr_init()
/u-boot/arch/m68k/cpu/mcf5227x/
A Dspeed.c33 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
46 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
58 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
75 ccm_t *ccm = (ccm_t *)MMAP_CCM; in get_clocks() local
109 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in get_clocks()
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c54 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in get_sys_clock() local
59 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
60 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
92 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_limp() local
102 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
105 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
107 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
115 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_exit_limp() local
119 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
122 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) in clock_exit_limp()
/u-boot/board/variscite/dart_6ul/
A Dspl.c93 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
95 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
96 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
97 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
98 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
99 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
100 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
101 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
102 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/u-boot/board/technexion/pico-imx6ul/
A Dspl.c99 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
101 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
102 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
103 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
104 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
105 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
106 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
107 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/solidrun/mx6cuboxi/
A Dmx6cuboxi.c209 reg = readl(&ccm->analog_pll_video); in setup_display()
214 writel(reg, &ccm->analog_pll_video); in setup_display()
239 reg = readl(&ccm->chsccdr); in setup_display()
246 writel(reg, &ccm->chsccdr); in setup_display()
698 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
699 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
700 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
701 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
702 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
703 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
[all …]

Completed in 48 milliseconds

12345