| /u-boot/lib/ |
| A D | fdtdec_common.c | 25 const int *cell; in fdtdec_get_int() local
29 cell = fdt_getprop(blob, node, prop_name, &len); in fdtdec_get_int()
30 if (cell && len >= sizeof(int)) { in fdtdec_get_int()
31 int val = fdt32_to_cpu(cell[0]); in fdtdec_get_int()
43 const int *cell; in fdtdec_get_uint() local
47 cell = fdt_getprop(blob, node, prop_name, &len); in fdtdec_get_uint()
48 if (cell && len >= sizeof(unsigned int)) { in fdtdec_get_uint()
49 unsigned int val = fdt32_to_cpu(cell[0]); in fdtdec_get_uint()
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| A D | fdtdec.c | 280 const char *cell; in fdtdec_get_is_enabled() local
290 if (cell) in fdtdec_get_is_enabled()
653 if (!cell) in get_prop_check_min_len()
659 return cell; in get_prop_check_min_len()
665 const u32 *cell; in fdtdec_get_int_array() local
689 if (!cell) in fdtdec_get_int_array_count()
848 const u8 *cell; in fdtdec_get_byte_array() local
860 const u8 *cell; in fdtdec_locate_byte_array() local
866 return cell; in fdtdec_locate_byte_array()
1674 if (!cell) { in fdtdec_decode_ram_size()
[all …]
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| /u-boot/drivers/pci/ |
| A D | pci_sandbox.c | 83 const fdt32_t *cell; in sandbox_pci_probe() local
87 cell = ofnode_get_property(dev_ofnode(dev), "sandbox,dev-info", &len); in sandbox_pci_probe()
88 if (!cell) in sandbox_pci_probe()
97 fdt32_to_cpu(cell[0]), fdt32_to_cpu(cell[1]), in sandbox_pci_probe()
98 fdt32_to_cpu(cell[2]), fdt32_to_cpu(cell[3])); in sandbox_pci_probe()
100 pdev = fdt32_to_cpu(cell[0]); in sandbox_pci_probe()
101 pfn = fdt32_to_cpu(cell[1]); in sandbox_pci_probe()
105 priv->vendev[devfn].vendor = fdt32_to_cpu(cell[2]); in sandbox_pci_probe()
106 priv->vendev[devfn].device = fdt32_to_cpu(cell[3]); in sandbox_pci_probe()
108 cell += FDT_DEV_INFO_CELLS; in sandbox_pci_probe()
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| /u-boot/drivers/core/ |
| A D | simple-bus.c | 25 u32 cell[3]; in simple_bus_post_bind()
28 ret = dev_read_u32_array(dev, "ranges", cell, ARRAY_SIZE(cell)); in simple_bus_post_bind()
32 plat->base = cell[0]; in simple_bus_post_bind()
33 plat->target = cell[1]; in simple_bus_post_bind()
34 plat->size = cell[2]; in simple_bus_post_bind()
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| A D | of_extra.c | 56 const fdt_addr_t *cell; in ofnode_decode_region() local
60 cell = ofnode_get_property(node, prop_name, &len); in ofnode_decode_region()
61 if (!cell || (len < sizeof(fdt_addr_t) * 2)) { in ofnode_decode_region()
62 debug("cell=%p, len=%d\n", cell, len); in ofnode_decode_region()
66 *basep = fdt_addr_to_cpu(*cell); in ofnode_decode_region()
67 *sizep = fdt_size_to_cpu(cell[1]); in ofnode_decode_region()
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| /u-boot/arch/powerpc/dts/ |
| A D | qoriq-fman-0.dtsi | 13 cell-index = <0>;
29 cell-index = <0x1>;
35 cell-index = <0x2>;
41 cell-index = <0x3>;
47 cell-index = <0x4>;
53 cell-index = <0x5>;
60 cell-index = <0x6>;
67 cell-index = <0x7>;
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| A D | qoriq-fman-1.dtsi | 13 cell-index = <1>;
29 cell-index = <0x1>;
35 cell-index = <0x2>;
41 cell-index = <0x3>;
47 cell-index = <0x4>;
53 cell-index = <0x5>;
60 cell-index = <0x6>;
67 cell-index = <0x7>;
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| A D | qoriq-fman3-0.dtsi | 13 cell-index = <0>;
29 cell-index = <0x2>;
35 cell-index = <0x3>;
41 cell-index = <0x4>;
47 cell-index = <0x5>;
53 cell-index = <0x6>;
59 cell-index = <0x7>;
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| A D | qoriq-fman3-1.dtsi | 13 cell-index = <1>;
29 cell-index = <0x2>;
35 cell-index = <0x3>;
41 cell-index = <0x4>;
47 cell-index = <0x5>;
53 cell-index = <0x6>;
59 cell-index = <0x7>;
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| A D | qoriq-fman3l-0.dtsi | 13 cell-index = <0>;
29 cell-index = <0x2>;
35 cell-index = <0x3>;
41 cell-index = <0x4>;
47 cell-index = <0x5>;
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| A D | qoriq-fman-1-10g-0.dtsi | 12 cell-index = <0x10>;
18 cell-index = <0x30>;
24 cell-index = <0x8>;
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| A D | qoriq-fman-0-10g-0.dtsi | 12 cell-index = <0x10>;
18 cell-index = <0x30>;
24 cell-index = <0x8>;
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| /u-boot/arch/arm/mach-socfpga/ |
| A D | pinmux_arria10.c | 17 const u32 *cell; in do_pinctr_pin() local
22 cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len); in do_pinctr_pin()
23 if (!cell || len <= 0) in do_pinctr_pin()
26 debug("%p %d\n", cell, len); in do_pinctr_pin()
28 offset = fdt32_to_cpu(*cell++); in do_pinctr_pin()
29 value = fdt32_to_cpu(*cell++); in do_pinctr_pin()
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| /u-boot/common/ |
| A D | common_fit.c | 15 const u32 *cell; in fdt_getprop_u32() local
18 cell = fdt_getprop(fdt, node, prop, &len); in fdt_getprop_u32()
19 if (!cell || len != sizeof(*cell)) in fdt_getprop_u32()
22 return fdt32_to_cpu(*cell); in fdt_getprop_u32()
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| /u-boot/arch/x86/cpu/ |
| A D | irq.c | 154 const u32 *cell; in create_pirq_routing_table() local
180 if (!cell || len != 8) in create_pirq_routing_table()
182 priv->link_base = fdt_addr_to_cpu(cell[0]); in create_pirq_routing_table()
183 priv->link_num = fdt_addr_to_cpu(cell[1]); in create_pirq_routing_table()
191 if (cell) { in create_pirq_routing_table()
209 map->link = fdt_addr_to_cpu(cell[0]); in create_pirq_routing_table()
210 map->offset = fdt_addr_to_cpu(cell[1]); in create_pirq_routing_table()
250 if (!cell || len % sizeof(struct pirq_routing)) in create_pirq_routing_table()
273 pr.bdf = fdt_addr_to_cpu(cell[0]); in create_pirq_routing_table()
274 pr.pin = fdt_addr_to_cpu(cell[1]); in create_pirq_routing_table()
[all …]
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| /u-boot/arch/arm/dts/ |
| A D | qoriq-fman3-0.dtsi | 13 cell-index = <0>;
28 cell-index = <0x2>;
34 cell-index = <0x3>;
40 cell-index = <0x4>;
46 cell-index = <0x5>;
52 cell-index = <0x6>;
58 cell-index = <0x7>;
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| A D | qoriq-fman3-0-10g-0.dtsi | 12 cell-index = <0x10>;
19 cell-index = <0x30>;
26 cell-index = <0x8>;
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| A D | qoriq-fman3-0-10g-1.dtsi | 12 cell-index = <0x11>;
19 cell-index = <0x31>;
26 cell-index = <0x9>;
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| A D | qoriq-fman3-0-1g-0.dtsi | 12 cell-index = <0x8>;
18 cell-index = <0x28>;
24 cell-index = <0>;
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| /u-boot/include/dm/ |
| A D | of.h | 119 static inline u64 of_read_number(const __be32 *cell, int size) in of_read_number() argument
123 r = (r << 32) | be32_to_cpu(*(cell++)); in of_read_number()
128 static inline unsigned long of_read_ulong(const __be32 *cell, int size) in of_read_ulong() argument
131 return of_read_number(cell, size); in of_read_ulong()
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| /u-boot/arch/microblaze/cpu/ |
| A D | timer.c | 55 u32 cell[2]; in timer_init() local
74 cell, ARRAY_SIZE(cell)); in timer_init()
78 irq = cell[0]; in timer_init()
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| /u-boot/test/dm/ |
| A D | ofnode.c | 112 const char cell[] = "#gpio-cells"; in dm_test_ofnode_phandle() local
119 ret = ofnode_count_phandle_with_args(node, "missing", cell, 0); in dm_test_ofnode_phandle()
123 ret = ofnode_count_phandle_with_args(node, prop, cell, 0); in dm_test_ofnode_phandle()
127 ret = ofnode_parse_phandle_with_args(node, "missing", cell, 0, 0, in dm_test_ofnode_phandle()
133 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 0, &args); in dm_test_ofnode_phandle()
137 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 1, &args); in dm_test_ofnode_phandle()
141 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 2, &args); in dm_test_ofnode_phandle()
146 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 3, &args); in dm_test_ofnode_phandle()
148 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 4, &args); in dm_test_ofnode_phandle()
152 ret = ofnode_parse_phandle_with_args(node, prop, cell, 0, 5, &args); in dm_test_ofnode_phandle()
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| /u-boot/drivers/pinctrl/ath79/ |
| A D | pinctrl_ar933x.c | 76 u32 cell[2]; in ar933x_pinctrl_get_periph_id() local
80 "interrupts", cell, ARRAY_SIZE(cell)); in ar933x_pinctrl_get_periph_id()
84 switch (cell[0]) { in ar933x_pinctrl_get_periph_id()
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| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | nvidia,tegra20-gpio.txt | 9 - #gpio-cells : Should be two. The first cell is the pin number and the
10 second cell is used to specify optional parameters:
14 The first cell is the GPIO number.
15 The second cell is used to specify flags:
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,irq-router.txt | 23 first cell is the register offset that controls the first PIRQ link routing.
24 The second cell is the total number of PIRQ links the router supports.
26 encoded as 2 cells a group for each link. The first cell is the PIRQ link
27 number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
30 link, as specified by the first cell of intel,pirq-link.
34 encoded as 3 cells a group for a device. The first cell is the device's PCI
36 The second cell is the PCI interrupt pin used by this device. The last cell
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