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Searched refs:cfg (Results 1 – 25 of 556) sorted by relevance

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/u-boot/drivers/phy/
A Dphy-core-mipi-dphy.c27 if (!cfg) in phy_mipi_dphy_get_default_config()
45 cfg->eot = 0; in phy_mipi_dphy_get_default_config()
67 cfg->ta_get = 5 * cfg->lpx; in phy_mipi_dphy_get_default_config()
68 cfg->ta_go = 4 * cfg->lpx; in phy_mipi_dphy_get_default_config()
69 cfg->ta_sure = 2 * cfg->lpx; in phy_mipi_dphy_get_default_config()
86 if (!cfg) in phy_mipi_dphy_config_validate()
104 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) in phy_mipi_dphy_config_validate()
113 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
148 if (cfg->ta_get != (5 * cfg->lpx)) in phy_mipi_dphy_config_validate()
151 if (cfg->ta_go != (4 * cfg->lpx)) in phy_mipi_dphy_config_validate()
[all …]
/u-boot/drivers/video/
A Dssd2828.c201 gpio_free(cfg->csx_pin); in ssd2828_enable_gpio()
206 gpio_free(cfg->csx_pin); in ssd2828_enable_gpio()
207 gpio_free(cfg->sck_pin); in ssd2828_enable_gpio()
212 gpio_free(cfg->csx_pin); in ssd2828_enable_gpio()
218 if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) { in ssd2828_enable_gpio()
230 if (cfg->sdo_pin != -1) in ssd2828_enable_gpio()
238 gpio_free(cfg->csx_pin); in ssd2828_free_gpio()
239 gpio_free(cfg->sck_pin); in ssd2828_free_gpio()
240 gpio_free(cfg->sdi_pin); in ssd2828_free_gpio()
242 if (cfg->sdo_pin != -1) in ssd2828_free_gpio()
[all …]
/u-boot/drivers/video/exynos/
A Dexynos_fb.c107 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
118 writel(cfg, &reg->dualrgb); in exynos_fimd_set_dualrgb()
125 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
137 unsigned int cfg = 0; in exynos_fimd_set_par() local
261 unsigned int cfg = 0; in exynos_set_trigger() local
273 unsigned int cfg = 0; in exynos_is_i80_frame_done() local
288 unsigned int cfg = 0; in exynos_fimd_lcd_on() local
300 unsigned int cfg = 0; in exynos_fimd_window_on() local
317 unsigned int cfg = 0; in exynos_fimd_lcd_off() local
327 unsigned int cfg = 0; in exynos_fimd_window_off() local
[all …]
/u-boot/drivers/power/
A Daxp209.c36 u8 cfg, current; in axp_set_dcdc2() local
50 current != cfg) { in axp_set_dcdc2()
51 if (current < cfg) in axp_set_dcdc2()
83 u8 cfg, reg; in axp_set_aldo2() local
95 reg |= AXP209_LDO24_LDO2_SET(reg, cfg); in axp_set_aldo2()
105 u8 cfg; in axp_set_aldo3() local
120 cfg = AXP209_VRC_LDO3_SLOPE_SET(cfg, AXP209_VRC_SLOPE); in axp_set_aldo3()
138 if (!(cfg & AXP209_OUTPUT_CTRL_LDO3)) { in axp_set_aldo3()
153 cfg = AXP209_LDO3_VOLTAGE_SET(cfg); in axp_set_aldo3()
170 u8 cfg, reg; in axp_set_aldo4() local
[all …]
A Daxp818.c39 ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg); in axp_set_dcdc1()
50 u8 cfg; in axp_set_dcdc2() local
61 ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg); in axp_set_dcdc2()
72 u8 cfg; in axp_set_dcdc3() local
83 ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg); in axp_set_dcdc3()
94 u8 cfg; in axp_set_dcdc5() local
105 ret = pmic_bus_write(AXP818_DCDC5_CTRL, cfg); in axp_set_dcdc5()
116 u8 cfg; in axp_set_aldo() local
153 u8 cfg; in axp_set_dldo() local
176 u8 cfg; in axp_set_eldo() local
[all …]
A Daxp809.c33 u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
39 ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg); in axp_set_dcdc1()
55 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc2() local
61 ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg); in axp_set_dcdc2()
72 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20); in axp_set_dcdc3() local
78 ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg); in axp_set_dcdc3()
89 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc4() local
98 ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); in axp_set_dcdc4()
115 ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); in axp_set_dcdc5()
126 u8 cfg; in axp_set_aldo() local
[all …]
A Daxp221.c31 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
37 ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg); in axp_set_dcdc1()
53 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc2() local
59 ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg); in axp_set_dcdc2()
70 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); in axp_set_dcdc3() local
76 ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg); in axp_set_dcdc3()
93 ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg); in axp_set_dcdc4()
110 ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg); in axp_set_dcdc5()
127 ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg); in axp_set_aldo1()
144 ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg); in axp_set_aldo2()
[all …]
/u-boot/drivers/clk/microchip/
A Dmpfs_clk_cfg.c60 struct mpfs_cfg_clock cfg; member
71 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; in mpfs_cfg_clk_recalc_rate() local
87 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; in mpfs_cfg_clk_set_rate() local
92 divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags); in mpfs_cfg_clk_set_rate()
98 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); in mpfs_cfg_clk_set_rate()
106 .cfg.id = _id, \
107 .cfg.name = _name, \
108 .cfg.shift = _shift, \
109 .cfg.width = _width, \
110 .cfg.table = _table, \
[all …]
/u-boot/drivers/ddr/altera/
A Dsdram_gen5.c295 u32 ctrl_cfg = cfg->ctrl_cfg; in sdr_get_ctrlcfg()
333 const int rows = get_errata_rows(cfg); in sdr_get_addr_rw()
346 const struct socfpga_sdram_config *cfg) in sdr_load_regs() argument
348 const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); in sdr_load_regs()
349 const u32 dram_addrw = sdr_get_addr_rw(cfg); in sdr_load_regs()
391 writel(cfg->port_cfg, &sdr_ctrl->port_cfg); in sdr_load_regs()
394 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); in sdr_load_regs()
438 writel(cfg->dram_odt, &sdr_ctrl->dram_odt); in sdr_load_regs()
464 sdr_load_regs(sdr_ctrl, cfg); in sdram_mmr_init_full()
467 writel(cfg->fpgaport_rst, in sdram_mmr_init_full()
[all …]
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dfsl_ls1_serdes.c43 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
49 cfg &= RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
50 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
55 cfg &= RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
56 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
64 if (unlikely(cfg == 0)) in serdes_get_first_lane()
68 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
79 u32 cfg; in serdes_init() local
83 cfg >>= sd_prctl_shift; in serdes_init()
84 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
[all …]
/u-boot/drivers/adc/
A Dexynos-adc.c40 unsigned int cfg; in exynos_adc_start_channel() local
43 cfg = readl(&regs->con2); in exynos_adc_start_channel()
44 cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK; in exynos_adc_start_channel()
46 writel(cfg, &regs->con2); in exynos_adc_start_channel()
49 cfg = readl(&regs->con1); in exynos_adc_start_channel()
61 unsigned int cfg; in exynos_adc_stop() local
64 cfg = readl(&regs->con1); in exynos_adc_stop()
65 cfg &= ~ADC_V2_CON1_STC_EN; in exynos_adc_stop()
67 writel(cfg, &regs->con1); in exynos_adc_stop()
78 unsigned int cfg; in exynos_adc_probe() local
[all …]
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c46 if (cfg == 0) in cm_basic_init()
68 writel(cfg->main_pll_fdbck, in cm_basic_init()
72 writel(cfg->main_pll_pllc0, in cm_basic_init()
74 writel(cfg->main_pll_pllc1, in cm_basic_init()
76 writel(cfg->main_pll_nocdiv, in cm_basic_init()
95 writel(cfg->per_pll_fdbck, in cm_basic_init()
99 writel(cfg->per_pll_pllc0, in cm_basic_init()
101 writel(cfg->per_pll_pllc1, in cm_basic_init()
103 writel(cfg->per_pll_emacctl, in cm_basic_init()
105 writel(cfg->per_pll_gpiodiv, in cm_basic_init()
[all …]
A Dclock_manager_gen5.c148 writel(cfg->mpuclk, in cm_basic_init()
156 writel(cfg->mainclk, in cm_basic_init()
160 writel(cfg->dbgatclk, in cm_basic_init()
168 writel(cfg->emac0clk, in cm_basic_init()
172 writel(cfg->emac1clk, in cm_basic_init()
216 writel(cfg->maindiv, in cm_basic_init()
219 writel(cfg->dbgdiv, in cm_basic_init()
226 writel(cfg->perdiv, in cm_basic_init()
229 writel(cfg->gpiodiv, in cm_basic_init()
326 writel(cfg->persrc, in cm_basic_init()
[all …]
/u-boot/drivers/pinctrl/renesas/
A Dsh_pfc.h422 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
428 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
434 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
439 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
444 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
449 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
454 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
460 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
465 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
470 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
[all …]
/u-boot/arch/arm/mach-exynos/
A Dsystem.c36 unsigned int cfg = 0; in exynos4_set_system_display() local
43 cfg = readl(&sysreg->display_ctrl); in exynos4_set_system_display()
44 cfg |= (1 << 1); in exynos4_set_system_display()
45 writel(cfg, &sysreg->display_ctrl); in exynos4_set_system_display()
52 unsigned int cfg = 0; in exynos5_set_system_display() local
59 cfg = readl(&sysreg->disp1blk_cfg); in exynos5_set_system_display()
60 cfg |= (1 << 15); in exynos5_set_system_display()
61 writel(cfg, &sysreg->disp1blk_cfg); in exynos5_set_system_display()
/u-boot/drivers/memory/
A Dti-aemif.c41 if (cfg->mode == AEMIF_MODE_NAND) { in aemif_configure()
46 } else if (cfg->mode == AEMIF_MODE_ONENAND) { in aemif_configure()
55 set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); in aemif_configure()
56 set_config_field(tmp, WR_SETUP, cfg->wr_setup); in aemif_configure()
57 set_config_field(tmp, WR_STROBE, cfg->wr_strobe); in aemif_configure()
58 set_config_field(tmp, WR_HOLD, cfg->wr_hold); in aemif_configure()
59 set_config_field(tmp, RD_SETUP, cfg->rd_setup); in aemif_configure()
60 set_config_field(tmp, RD_STROBE, cfg->rd_strobe); in aemif_configure()
61 set_config_field(tmp, RD_HOLD, cfg->rd_hold); in aemif_configure()
62 set_config_field(tmp, TURN_AROUND, cfg->turn_around); in aemif_configure()
[all …]
/u-boot/board/gateworks/gw_ventana/
A Deeprom.c153 while (cfg->name) { in get_config()
155 return cfg; in get_config()
156 cfg++; in get_config()
182 cfg = econfig; in do_econfig()
183 while (cfg->name) { in do_econfig()
184 printf("%s: %d\n", cfg->name, in do_econfig()
186 cfg++; in do_econfig()
224 cfg = get_config(argv[1]); in do_econfig()
225 if (cfg) { in do_econfig()
236 cfg = get_config(argv[1]); in do_econfig()
[all …]
/u-boot/include/fsl-mc/
A Dfsl_dpni.h51 #define DPNI_PREP_CFG(param, cfg) \ argument
63 #define DPNI_EXT_CFG(param, cfg) \ argument
75 #define DPNI_CMD_CREATE(cmd, cfg) \ argument
87 #define DPNI_CMD_SET_POOLS(cmd, cfg) \ argument
132 #define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ argument
162 #define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ argument
535 const struct dpni_cfg *cfg,
588 const struct dpni_pools_cfg *cfg);
678 int dpni_extract_cfg(struct dpni_cfg *cfg,
750 struct dpni_error_cfg *cfg);
[all …]
A Dfsl_dpmac.h34 #define DPMAC_CMD_CREATE(cmd, cfg) \ argument
52 #define DPMAC_CMD_MDIO_READ(cmd, cfg) \ argument
55 MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
63 #define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ argument
71 #define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ argument
78 #define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ argument
82 MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \
211 const struct dpmac_cfg *cfg,
294 struct dpmac_mdio_cfg *cfg);
308 struct dpmac_mdio_cfg *cfg);
[all …]
/u-boot/drivers/ddr/imx/imx8m/
A Dhelper.c137 struct dram_cfg_param *cfg; in dram_config_save() local
152 saved_timing->ddrc_cfg = cfg; in dram_config_save()
156 cfg++; in dram_config_save()
160 saved_timing->ddrphy_cfg = cfg; in dram_config_save()
164 cfg++; in dram_config_save()
168 saved_timing->ddrphy_trained_csr = cfg; in dram_config_save()
170 cfg->reg = ddrphy_trained_csr[i].reg; in dram_config_save()
171 cfg->val = ddrphy_trained_csr[i].val; in dram_config_save()
172 cfg++; in dram_config_save()
176 saved_timing->ddrphy_pie = cfg; in dram_config_save()
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch3_serdes.c58 return cfg; in serdes_get_number()
90 u32 cfg = 0; in serdes_get_first_lane() local
120 cfg = serdes_get_number(sd, cfg); in serdes_get_first_lane()
123 if (cfg == 0) in serdes_get_first_lane()
138 u32 cfg; in serdes_init() local
147 cfg >>= sd_prctl_shift; in serdes_init()
149 cfg = serdes_get_number(sd, cfg); in serdes_init()
150 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
613 u32 cfg; in serdes_set_env() local
616 cfg >>= sd_prctl_shift; in serdes_set_env()
[all …]
/u-boot/drivers/net/octeontx/
A Dbgx.c205 u64 cfg; in bgx_lmac_rx_tx_enable() local
267 u64 cfg; in get_qlm_for_bgx() local
296 if (cfg) { in get_qlm_for_bgx()
306 u64 cfg; in bgx_lmac_sgmii_init() local
375 u64 cfg; in bgx_lmac_sgmii_set_link_speed() local
453 u64 cfg; in bgx_lmac_xaui_init() local
506 cfg = cfg & ~(SPU_AN_CTL_XNP_EN); in bgx_lmac_xaui_init()
508 cfg = cfg | (SPU_AN_CTL_AN_EN); in bgx_lmac_xaui_init()
510 cfg = cfg & ~(SPU_AN_CTL_AN_EN); in bgx_lmac_xaui_init()
653 u64 cfg; in bgx_xaui_check_link() local
[all …]
/u-boot/include/
A Daxp209.h51 #define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \ argument
53 ((cfg) & AXP209_VRC_DCDC2_MASK))
54 #define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \ argument
56 ((cfg) & AXP209_VRC_LDO3_MASK))
60 #define AXP209_LDO24_LDO2_SET(reg, cfg) \ argument
62 (((cfg) << 4) & AXP209_LDO24_LDO2_MASK))
63 #define AXP209_LDO24_LDO4_SET(reg, cfg) \ argument
65 (((cfg) << 0) & AXP209_LDO24_LDO4_MASK))
/u-boot/drivers/mmc/
A Dmmc_legacy.c112 printf("%s: %d", m->cfg->name, m->block_dev.devnum); in print_mmc_devices()
145 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) in mmc_create() argument
153 if (mmc->cfg) { in mmc_create()
158 mmc->cfg = cfg; in mmc_create()
168 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) in mmc_create() argument
174 if (cfg == NULL || cfg->f_min == 0 || in mmc_create()
175 cfg->f_max == 0 || cfg->b_max == 0) in mmc_create()
179 if (cfg->ops == NULL || cfg->ops->send_cmd == NULL) in mmc_create()
187 mmc->cfg = cfg; in mmc_create()
205 bdesc->part_type = mmc->cfg->part_type; in mmc_create()
/u-boot/drivers/dma/
A Dti-edma3.c60 if (cfg->complete_code < 32) in qedma3_start()
324 __raw_writel(cfg->opt, &rg->opt); in edma3_slot_configure()
325 __raw_writel(cfg->src, &rg->src); in edma3_slot_configure()
326 __raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt); in edma3_slot_configure()
327 __raw_writel(cfg->dst, &rg->dst); in edma3_slot_configure()
328 __raw_writel((cfg->dst_bidx << 16) | in edma3_slot_configure()
330 __raw_writel((cfg->bcntrld << 16) | in edma3_slot_configure()
332 __raw_writel((cfg->dst_cidx << 16) | in edma3_slot_configure()
352 if (cfg->complete_code < 32) { in edma3_check_for_transfer()
355 inum = 1 << cfg->complete_code; in edma3_check_for_transfer()
[all …]

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