| /u-boot/drivers/video/sunxi/ |
| A D | tve_common.c | 22 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0); in tvencoder_mode_set()
34 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0); in tvencoder_mode_set()
60 writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0); in tvencoder_mode_set()
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| /u-boot/arch/mips/mach-mtmips/include/mach/ |
| A D | ddr.h | 26 u32 cfg0; member
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| /u-boot/arch/mips/mach-mtmips/ |
| A D | ddr_init.c | 86 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG); in mc_ddr_init()
204 static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, in mc_sdr_init() argument
211 writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG); in mc_sdr_init()
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| /u-boot/arch/arm/mach-imx/ |
| A D | mmdc_size.c | 21 u32 cfg0; member
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| /u-boot/drivers/pci/ |
| A D | pcie_layerscape_rc.c | 167 *paddress = pcie_rc->cfg0 + offset; in ls_pcie_conf_address()
340 pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start, in ls_pcie_probe()
343 pcie_rc->cfg1 = pcie_rc->cfg0 + in ls_pcie_probe()
350 (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0, in ls_pcie_probe()
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| A D | pcie_layerscape.h | 157 void __iomem *cfg0; member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | tve.h | 29 u32 cfg0; /* 0x004 */ member
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| A D | dram_sun50i_h616.h | 47 u32 cfg0; /* 0x0 */ member
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| A D | dram_sun50i_h6.h | 52 u32 cfg0; /* 0x0 */ member
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | fdt.c | 168 u32 cfg0 = in_be32(&cpc->cpccfg0); in ft_fixup_l3cache() local
170 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; in ft_fixup_l3cache()
171 num_ways = CPC_CFG0_NUM_WAYS(cfg0); in ft_fixup_l3cache()
172 line_size = CPC_CFG0_LINE_SZ(cfg0); in ft_fixup_l3cache()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h6.c | 108 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
116 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
117 writel(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
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| A D | dram_sun50i_h616.c | 46 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
54 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
55 writel_relaxed(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
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| A D | dram_sunxi_dw.c | 97 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
105 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
106 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | fsl_liodn.h | 226 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
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| A D | immap_85xx.h | 2732 u32 cfg0; /* cfg register 0 */ member
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| /u-boot/arch/arm/include/asm/arch-mx25/ |
| A D | imx-regs.h | 54 u32 cfg0; /* configuration 0 */ member
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| /u-boot/arch/arm/lib/ |
| A D | asm-offsets.c | 49 DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); in main()
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | imx-regs.h | 139 u32 cfg0; member
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| /u-boot/arch/arm/include/asm/arch-mx31/ |
| A D | imx-regs.h | 511 u32 cfg0; member
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| /u-boot/arch/arm/include/asm/arch-mx7/ |
| A D | imx-regs.h | 918 u32 cfg0; member
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| /u-boot/arch/arm/include/asm/arch-mx7ulp/ |
| A D | imx-regs.h | 1005 u32 cfg0; member
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| /u-boot/arch/arm/dts/ |
| A D | ast2600.dtsi | 419 pcie_cfg0: cfg0@80 {
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