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Searched refs:cfg_tmp (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch2_serdes.c152 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
200 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()
216 cfg_tmp = (cfg_rcw5 >> 20) & 0x3; in setup_serdes_volt()
263 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()
275 if (!(cfg_tmp == 0x3 && i == 1)) { in setup_serdes_volt()
289 cfg_tmp = (cfg_rcw5 >> 20) & 0x3; in setup_serdes_volt()
301 if (!(cfg_tmp == 0x3 && i == 1)) { in setup_serdes_volt()
319 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()
339 cfg_tmp = (cfg_rcw5 >> 20) & 0x3; in setup_serdes_volt()
380 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()
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A Dfsl_lsch3_serdes.c290 u32 cfg_tmp; in do_enabled_lanes_reset() local
412 u32 cfg_tmp; in setup_serdes_volt() local
447 cfg_tmp = cfg_rcwsrds1 & 0x3; in setup_serdes_volt()
453 cfg_tmp >>= 2; in setup_serdes_volt()
459 cfg_tmp >>= 4; in setup_serdes_volt()
489 cfg_tmp >>= 2; in setup_serdes_volt()
494 cfg_tmp >>= 4; in setup_serdes_volt()
508 cfg_tmp >>= 2; in setup_serdes_volt()
514 cfg_tmp >>= 4; in setup_serdes_volt()
537 cfg_tmp >>= 2; in setup_serdes_volt()
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