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Searched refs:cgu (Results 1 – 7 of 7) sorted by relevance

/u-boot/arch/mips/dts/
A Djz4780.dtsi3 #include <dt-bindings/clock/jz4780-cgu.h>
39 cgu: jz4780-cgu@10000000 { label
40 compatible = "ingenic,jz4780-cgu";
55 clocks = <&cgu JZ4780_CLK_MSC0>;
63 clocks = <&cgu JZ4780_CLK_MSC1>;
77 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
91 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
105 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
119 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
151 clocks = <&cgu JZ4780_CLK_NEMC>;
[all …]
/u-boot/doc/device-tree-bindings/clock/
A Dsnps,hsdk-cgu.txt8 - compatible: should be "snps,hsdk-cgu-clock"
15 preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
20 cgu_clk: cgu-clk@f0000000 {
21 compatible = "snps,hsdk-cgu-clock";
/u-boot/arch/arc/dts/
A Dhsdk-common.dtsi9 #include "dt-bindings/clock/snps,hsdk-cgu.h"
61 cgu_clk: cgu-clk@f0000000 {
62 compatible = "snps,hsdk-cgu-clock";
/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dpll.c442 static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num) in cgu_mux_init() argument
449 writel(selectplls[cgu[i].pll] << cgu[i].pll_shift, in cgu_mux_init()
450 cpm_regs + cgu[i].reg); in cgu_mux_init()
/u-boot/drivers/clk/
A DMakefile30 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
A DKconfig102 bool "Enable cgu clock driver for HSDK boards"
105 Enable this to support the cgu clocks on Synopsys ARC HSDK and
/u-boot/
A DMAINTAINERS86 F: drivers/clk/clk-hsdk-cgu.c
87 F: include/dt-bindings/clock/snps,hsdk-cgu.h
88 F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt

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