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Searched refs:ch (Results 1 – 25 of 193) sorted by relevance

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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
A Dsdram_common.h71 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
72 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
73 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
78 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) argument
80 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) argument
81 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) argument
84 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) argument
85 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) argument
86 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) argument
87 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) argument
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/u-boot/arch/x86/cpu/quark/
A Dsmc.c279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1591 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
[all …]
/u-boot/arch/arm/mach-nexell/
A Dtimer.c47 #define TCFG0_BIT_CH(ch) ((ch) == 0 || (ch) == 1 ? 0 : 8) argument
48 #define TCFG1_BIT_CH(ch) ((ch) * 4) argument
49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) argument
50 #define TINT_CH(ch) (ch) argument
51 #define TINT_CSTAT_BIT_CH(ch) ((ch) + 5) argument
81 writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), in timer_start()
97 writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), in timer_stop()
148 timer_stop(base, ch); in timer_init()
150 timer_count(base, ch, tcnt); in timer_init()
151 timer_start(base, ch); in timer_init()
[all …]
/u-boot/board/freescale/ls1021aqds/
A Ddcu.c20 static int select_i2c_ch_pca9547(u8 ch, int bus_num) in select_i2c_ch_pca9547() argument
33 ret = dm_i2c_write(dev, 0, &ch, 1); in select_i2c_ch_pca9547()
35 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); in select_i2c_ch_pca9547()
65 u8 ch; in platform_dcu_init() local
79 ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1); in platform_dcu_init()
85 ch &= 0x1F; in platform_dcu_init()
86 ch |= 0xA0; in platform_dcu_init()
91 1, &ch, 1); in platform_dcu_init()
97 ch &= 0x1F; in platform_dcu_init()
98 ch |= 0xA0; in platform_dcu_init()
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/u-boot/lib/
A Dcharset.c39 s32 ch = 0; in get_code() local
42 if (!ch) in get_code()
44 if (ch >= 0xc2 && ch <= 0xf4) { in get_code()
53 if (ch < 0x80 || ch > 0xbf) in get_code()
65 if (ch < 0x80 || ch > 0xbf) in get_code()
72 if (ch < 0x80 || ch > 0xbf) in get_code()
79 return ch; in get_code()
113 int ch; in read_console() local
116 if (ch < 0) in read_console()
117 ch = 0; in read_console()
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A Dtiny-printf.c53 char ch; in string() local
55 while ((ch = *s++)) in string()
56 out(info, ch); in string()
201 char ch; in _vprintf() local
215 ch = *(fmt++); in _vprintf()
216 if (ch == '-') in _vprintf()
224 if (ch >= '0' && ch <= '9') { in _vprintf()
226 while (ch >= '0' && ch <= '9') { in _vprintf()
228 ch = *fmt++; in _vprintf()
240 switch (ch) { in _vprintf()
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/u-boot/net/
A Dmdio-mux-uclass.c65 struct udevice *mux = ch->parent; in mmux_change_sel()
91 struct udevice *mux = ch->parent; in mmux_read()
96 err = mmux_change_sel(ch, true); in mmux_read()
101 mmux_change_sel(ch, false); in mmux_read()
110 struct udevice *mux = ch->parent; in mmux_write()
115 err = mmux_change_sel(ch, true); in mmux_write()
120 mmux_change_sel(ch, false); in mmux_write()
126 static int mmux_reset(struct udevice *ch) in mmux_reset() argument
128 struct udevice *mux = ch->parent; in mmux_reset()
137 err = mmux_change_sel(ch, true); in mmux_reset()
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/u-boot/include/
A Dhexdump.h37 static inline int hex_to_bin(char ch) in hex_to_bin() argument
39 if ((ch >= '0') && (ch <= '9')) in hex_to_bin()
40 return ch - '0'; in hex_to_bin()
41 ch = tolower(ch); in hex_to_bin()
42 if ((ch >= 'a') && (ch <= 'f')) in hex_to_bin()
43 return ch - 'a' + 10; in hex_to_bin()
A Ddebug_uart.h77 void printch(int ch);
136 static inline void _printch(int ch) \
138 if (ch == '\n') \
140 _debug_uart_putc(ch); \
143 void printch(int ch) \
145 _printch(ch); \
/u-boot/arch/arm/mach-rockchip/
A Dsdram.c83 u32 ch; in rockchip_sdram_size() local
94 for (ch = 0; ch < ch_num; ch++) { in rockchip_sdram_size()
95 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
107 SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
112 SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
115 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
119 SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
124 SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
127 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
135 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & in rockchip_sdram_size()
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/u-boot/common/
A Dkgdb.c121 if (ch >= 'a' && ch <= 'f') in hex()
122 return ch-'a'+10; in hex()
123 if (ch >= '0' && ch <= '9') in hex()
124 return ch-'0'; in hex()
125 if (ch >= 'A' && ch <= 'F') in hex()
137 unsigned char ch; in mem2hex() local
149 ch = *tmp++; in mem2hex()
232 unsigned char ch; in getpacket() local
240 putc(ch); in getpacket()
253 if (ch == '#') in getpacket()
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/u-boot/drivers/clk/uniphier/
A Dclk-uniphier-mio.c19 #define UNIPHIER_MIO_CLK_SD(_id, ch) \ argument
35 .reg = 0x30 + 0x200 * (ch), \
58 UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
60 #define UNIPHIER_MIO_CLK_USB2(id, ch) \ argument
61 UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
63 #define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \ argument
64 UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
/u-boot/arch/arm/mach-uniphier/clk/
A Dclk-ld11.c37 int ch; in uniphier_ld11_clk_init() local
39 for (ch = 0; ch < 3; ch++) { in uniphier_ld11_clk_init()
42 writel(0x82280600, phyctrl + 8 * ch); in uniphier_ld11_clk_init()
43 writel(0x00000106, phyctrl + 8 * ch + 4); in uniphier_ld11_clk_init()
/u-boot/drivers/serial/
A Dserial_efi.c52 int ret, ch; in serial_efi_getc() local
59 ch = priv->key.unicode_char; in serial_efi_getc()
66 if (!ch && priv->key.scan_code == 8) in serial_efi_getc()
67 ch = 8; in serial_efi_getc()
68 debug(" [%x %x %x] ", ch, priv->key.unicode_char, priv->key.scan_code); in serial_efi_getc()
70 return ch; in serial_efi_getc()
73 static int serial_efi_putc(struct udevice *dev, const char ch) in serial_efi_putc() argument
79 ucode[0] = ch; in serial_efi_putc()
114 static inline void _debug_uart_putc(int ch) in _debug_uart_putc() argument
119 ucode[0] = ch; in _debug_uart_putc()
A Darm_dcc.c100 int ch; in arm_dcc_getc() local
106 read_dcc(ch); in arm_dcc_getc()
108 return ch; in arm_dcc_getc()
111 static int arm_dcc_putc(struct udevice *dev, char ch) in arm_dcc_putc() argument
124 write_dcc(ch); in arm_dcc_putc()
168 static inline void _debug_uart_putc(int ch) in _debug_uart_putc() argument
170 arm_dcc_putc(NULL, ch); in _debug_uart_putc()
/u-boot/drivers/video/imx/
A Dipu_regs.h311 #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) argument
316 #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) argument
317 #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) argument
318 #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) argument
327 #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) argument
328 #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) argument
365 switch (ch) { in dc_ch_offset()
369 return &DC_REG->dc_ch0_1_2[ch]; in dc_ch_offset()
384 #define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2]) argument
386 #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf) argument
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A Dipu.h83 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) argument
84 #define IPU_CHAN_ID(ch) (ch >> 24) argument
85 #define IPU_CHAN_ALT(ch) (ch & 0x02000000) argument
86 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) argument
87 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) argument
88 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) argument
89 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) argument
/u-boot/scripts/
A Dbin2c.c14 int ch, total = 0; in main() local
22 while ((ch = getchar()) != EOF) { in main()
24 printf("\\x%02x", ch); in main()
29 } while (ch != EOF); in main()
/u-boot/drivers/reset/
A Dreset-uniphier.c102 #define UNIPHIER_MIO_RESET_SD(id, ch) \ argument
103 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
105 #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ argument
109 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
111 #define UNIPHIER_MIO_RESET_USB2(id, ch) \ argument
141 #define UNIPHIER_PERI_RESET_UART(id, ch) \ argument
142 UNIPHIER_RESETX((id), 0x114, 19 + (ch))
144 #define UNIPHIER_PERI_RESET_I2C(id, ch) \ argument
145 UNIPHIER_RESETX((id), 0x114, 5 + (ch))
147 #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ argument
[all …]
/u-boot/arch/arm/mach-uniphier/bcu/
A Dbcu-ld4.c13 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) macro
27 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
30 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
33 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
/u-boot/arch/arm/mach-uniphier/dram/
A Dumc-ld4.c40 static int umc_get_rank(int ch) in umc_get_rank() argument
42 return ch; /* ch0: rank0, ch1: rank1 for this SoC */ in umc_get_rank()
144 int freq, unsigned long size, bool ddr3plus, int ch) in umc_ch_init() argument
159 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
173 int ch, ret; in uniphier_ld4_umc_init() local
175 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_ld4_umc_init()
177 bd->dram_ch[ch].size, in uniphier_ld4_umc_init()
178 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); in uniphier_ld4_umc_init()
180 pr_err("failed to initialize UMC ch%d\n", ch); in uniphier_ld4_umc_init()
A Dumc-sld8.c43 static int umc_get_rank(int ch) in umc_get_rank() argument
45 return ch; /* ch0: rank0, ch1: rank1 for this SoC */ in umc_get_rank()
147 int freq, unsigned long size, bool ddr3plus, int ch) in umc_ch_init() argument
162 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
176 int ch, ret; in uniphier_sld8_umc_init() local
178 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_sld8_umc_init()
180 bd->dram_ch[ch].size, in uniphier_sld8_umc_init()
181 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); in uniphier_sld8_umc_init()
183 pr_err("failed to initialize UMC ch%d\n", ch); in uniphier_sld8_umc_init()
/u-boot/drivers/video/
A Dvidconsole-uclass.c40 return ops->putc_xy(dev, x, y, ch); in vidconsole_putc_xy()
235 switch (ch) { in vidconsole_escape_char()
265 if (!isalpha(ch)) in vidconsole_escape_char()
275 switch (ch) { in vidconsole_escape_char()
295 if (ch == 'A' || ch == 'F') in vidconsole_escape_char()
297 if (ch == 'C') in vidconsole_escape_char()
299 if (ch == 'D') in vidconsole_escape_char()
301 if (ch == 'B' || ch == 'E') in vidconsole_escape_char()
303 if (ch == 'E' || ch == 'F') in vidconsole_escape_char()
500 priv->last_ch = ch; in vidconsole_output_glyph()
[all …]
/u-boot/lib/efi_loader/
A Defi_console.c703 s32 ch; in efi_cin_read_key() local
713 ch = '?'; in efi_cin_read_key()
715 switch (ch) { in efi_cin_read_key()
732 ch = getchar(); in efi_cin_read_key()
733 switch (ch) { in efi_cin_read_key()
751 switch (ch) { in efi_cin_read_key()
763 switch (ch) { in efi_cin_read_key()
786 switch (ch) { in efi_cin_read_key()
819 ch = 0x08; in efi_cin_read_key()
830 if (ch >= 0x01 && ch <= 0x1f) { in efi_cin_read_key()
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