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Searched refs:channel (Results 1 – 25 of 277) sorted by relevance

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/u-boot/drivers/dma/
A DMCD_dmaApi.c312 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_dmaStatus()
375 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_startDma()
449 if (channel < 8 && channel >= 0) { in MCD_startDma()
474 channel); in MCD_startDma()
483 channel); in MCD_startDma()
636 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_XferProgrQuery()
808 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_killDma()
845 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_continDma()
899 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_pauseDma()
929 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_resumeDma()
[all …]
A Dlpc32xx_dma.c96 int lpc32xx_dma_start_xfer(unsigned int channel, in lpc32xx_dma_start_xfer() argument
100 (channel >= DMA_NO_OF_CHANNELS))) { in lpc32xx_dma_start_xfer()
104 writel(BIT_MASK(channel), &dma->int_tc_clear); in lpc32xx_dma_start_xfer()
105 writel(BIT_MASK(channel), &dma->int_err_clear); in lpc32xx_dma_start_xfer()
108 writel(desc->next_lli, &dma->dma_chan[channel].lli); in lpc32xx_dma_start_xfer()
110 writel(config, &dma->dma_chan[channel].config_ch); in lpc32xx_dma_start_xfer()
115 int lpc32xx_dma_wait_status(unsigned int channel) in lpc32xx_dma_wait_status() argument
121 if (unlikely(channel >= DMA_NO_OF_CHANNELS)) { in lpc32xx_dma_wait_status()
130 if (reg & BIT_MASK(channel)) in lpc32xx_dma_wait_status()
143 pr_err("DMA error on channel %d\n", channel); in lpc32xx_dma_wait_status()
[all …]
A Dapbh_dma.c33 int mxs_dma_validate_chan(int channel) in mxs_dma_validate_chan() argument
37 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_validate_chan()
40 pchan = mxs_dma_channels + channel; in mxs_dma_validate_chan()
76 ret = mxs_dma_validate_chan(channel); in mxs_dma_read_semaphore()
125 pchan = mxs_dma_channels + channel; in mxs_dma_enable()
290 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_request()
318 int mxs_dma_release(int channel) in mxs_dma_release() argument
608 ret = mxs_dma_request(channel); in mxs_dma_init_channel()
612 channel); in mxs_dma_init_channel()
616 mxs_dma_reset(channel); in mxs_dma_init_channel()
[all …]
A DMCD_tasksInit.c22 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainNoEu() argument
24 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainNoEu()
52 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainNoEu()
60 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleNoEu() argument
83 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleNoEu()
90 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainEu() argument
123 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainEu()
158 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleEu()
164 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaENetRcv() argument
187 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaENetRcv()
[all …]
/u-boot/arch/powerpc/dts/
A Delo3-dma-0.dtsi15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
21 compatible = "fsl,eloplus-dma-channel";
25 dma-channel@100 {
26 compatible = "fsl,eloplus-dma-channel";
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
A Delo3-dma-1.dtsi15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
21 compatible = "fsl,eloplus-dma-channel";
25 dma-channel@100 {
26 compatible = "fsl,eloplus-dma-channel";
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
/u-boot/arch/x86/cpu/quark/
A Dmrc_util.c156 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
172 channel * DDRIODQ_CH_OFFSET); in set_rcvn()
183 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
228 channel * DDRIODQ_CH_OFFSET; in get_rcvn()
1000 if (channel > 0) { in get_addr()
1125 channel, rank, rcvn); in find_rising_edge()
1354 uint8_t channel; in clear_pointers() local
1359 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1447 uint8_t channel; in print_timings() local
1456 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
[all …]
A Dmrc_util.h87 void set_rcvn(uint8_t channel, uint8_t rank,
90 void set_rdqs(uint8_t channel, uint8_t rank,
93 void set_wdqs(uint8_t channel, uint8_t rank,
96 void set_wdq(uint8_t channel, uint8_t rank,
99 void set_wcmd(uint8_t channel, uint32_t pi_count);
100 uint32_t get_wcmd(uint8_t channel);
102 uint32_t get_wclk(uint8_t channel, uint8_t rank);
104 uint32_t get_wctl(uint8_t channel, uint8_t rank);
106 uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
108 uint32_t get_addr(uint8_t channel, uint8_t rank);
[all …]
/u-boot/drivers/pwm/
A Dpwm-meson.c115 if (channel->polarity) in meson_pwm_set_config()
147 channel->hi = cnt; in meson_pwm_set_config()
148 channel->lo = 0; in meson_pwm_set_config()
151 channel->hi = 0; in meson_pwm_set_config()
152 channel->lo = cnt; in meson_pwm_set_config()
165 channel->hi = duty_cnt; in meson_pwm_set_config()
173 if (channel->enabled) { in meson_pwm_set_config()
194 if (!channel->configured) in meson_pwm_set_enable()
198 if (channel->enabled) in meson_pwm_set_enable()
218 if (!channel->enabled) in meson_pwm_set_enable()
[all …]
A Dexynos_pwm.c29 if (channel >= 5) in exynos_pwm_set_config()
32 __func__, dev->name, channel, period_ns, duty_ns); in exynos_pwm_set_config()
35 prescaler = (channel < 2 ? val : (val >> 8)) & 0xff; in exynos_pwm_set_config()
41 if (channel < 4) { in exynos_pwm_set_config()
46 offset = channel * 3; in exynos_pwm_set_config()
52 tcon |= TCON_UPDATE(channel); in exynos_pwm_set_config()
53 if (channel < 4) in exynos_pwm_set_config()
54 tcon |= TCON_AUTO_RELOAD(channel); in exynos_pwm_set_config()
59 tcon &= ~TCON_UPDATE(channel); in exynos_pwm_set_config()
72 if (channel >= 4) in exynos_pwm_set_enable()
[all …]
A Dsandbox_pwm.c42 if (channel >= NUM_CHANNELS) in sandbox_pwm_get_config()
44 chan = &priv->chan[channel]; in sandbox_pwm_get_config()
53 static int sandbox_pwm_set_config(struct udevice *dev, uint channel, in sandbox_pwm_set_config() argument
59 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()
61 chan = &priv->chan[channel]; in sandbox_pwm_set_config()
68 static int sandbox_pwm_set_enable(struct udevice *dev, uint channel, in sandbox_pwm_set_enable() argument
74 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()
76 chan = &priv->chan[channel]; in sandbox_pwm_set_enable()
82 static int sandbox_pwm_set_invert(struct udevice *dev, uint channel, in sandbox_pwm_set_invert() argument
88 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
[all …]
A Dtegra_pwm.c18 static int tegra_pwm_set_config(struct udevice *dev, uint channel, in tegra_pwm_set_config() argument
26 if (channel >= 4) in tegra_pwm_set_config()
28 debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); in tegra_pwm_set_config()
36 writel(reg, &regs[channel].control); in tegra_pwm_set_config()
42 static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable) in tegra_pwm_set_enable() argument
47 if (channel >= 4) in tegra_pwm_set_enable()
49 debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel); in tegra_pwm_set_enable()
50 clrsetbits_le32(&regs[channel].control, PWM_ENABLE_MASK, in tegra_pwm_set_enable()
A Dpwm-uclass.c11 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity) in pwm_set_invert() argument
18 return ops->set_invert(dev, channel, polarity); in pwm_set_invert()
21 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns, in pwm_set_config() argument
29 return ops->set_config(dev, channel, period_ns, duty_ns); in pwm_set_config()
32 int pwm_set_enable(struct udevice *dev, uint channel, bool enable) in pwm_set_enable() argument
39 return ops->set_enable(dev, channel, enable); in pwm_set_enable()
A Dpwm-mtk.c52 u32 offset = mtk_pwm_reg_offset[channel]; in mtk_pwm_w32()
57 static int mtk_pwm_set_config(struct udevice *dev, uint channel, in mtk_pwm_set_config() argument
70 do_div(resolution, clk_get_rate(&priv->pwm_clks[channel])); in mtk_pwm_set_config()
82 clk_get_rate(&priv->pwm_clks[channel])); in mtk_pwm_set_config()
85 clk_enable(&priv->pwm_clks[channel]); in mtk_pwm_set_config()
92 if (priv->soc->pwm45_fixup && channel > 2) { in mtk_pwm_set_config()
104 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv); in mtk_pwm_set_config()
105 mtk_pwm_w32(dev, channel, reg_width, cnt_period); in mtk_pwm_set_config()
106 mtk_pwm_w32(dev, channel, reg_thres, cnt_duty); in mtk_pwm_set_config()
118 val |= BIT(channel); in mtk_pwm_set_enable()
[all …]
A Dpwm-ti-ehrpwm.c123 if (channel >= TI_EHRPWM_NUM_CHANNELS) in ti_ehrpwm_set_invert()
183 if (channel == 1) { in ti_ehrpwm_configure_polarity()
187 if (priv->polarity_reversed[channel]) in ti_ehrpwm_configure_polarity()
195 if (priv->polarity_reversed[channel]) in ti_ehrpwm_configure_polarity()
218 if (channel >= TI_EHRPWM_NUM_CHANNELS) in ti_ehrpwm_set_config()
240 channel, period_ns, duty_ns); in ti_ehrpwm_set_config()
253 if (i == channel) in ti_ehrpwm_set_config()
290 if (channel == 1) in ti_ehrpwm_set_config()
307 if (channel >= TI_EHRPWM_NUM_CHANNELS) in ti_ehrpwm_disable()
311 if (channel) { in ti_ehrpwm_disable()
[all …]
/u-boot/drivers/ram/rockchip/
A Dsdram_rk3399.c237 channel &= 0x1; in rkclk_ddr_reset()
1649 u32 channel; in switch_to_phy_index1() local
1678 for (channel = 0; channel < ch_count; channel++) { in switch_to_phy_index1()
2472 u32 channel; in lpddr4_set_phy() local
2474 for (channel = 0; channel < 2; channel++) in lpddr4_set_phy()
2476 channel); in lpddr4_set_phy()
2483 u32 channel; in lpddr4_set_ctl() local
2524 for (channel = 0; channel < 2; channel++) { in lpddr4_set_ctl()
2772 for (channel = 0; channel < 2; channel++) { in calculate_stride()
2923 for (channel = 0; channel < 2; channel++) { in sdram_init()
[all …]
A Dsdram_rk3288.c126 int channel) in phy_pctrl_reset() argument
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
231 mask = channel ? in ddr_set_en_bst_odt()
636 } else if ((channel == 1) && in sdram_rank_bw_detect()
658 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
788 int channel; in sdram_init() local
809 for (channel = 0; channel < 2; channel++) { in sdram_init()
815 if (channel) in sdram_init()
[all …]
A Dsdram_rk3188.c126 int channel) in phy_pctrl_reset() argument
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
389 ddr_set_enable(grf, channel, 1); in set_bandwidth_ratio()
399 ddr_set_enable(grf, channel, 0); in set_bandwidth_ratio()
604 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
716 int channel; in sdram_init() local
732 for (channel = 0; channel < 1; channel++) { in sdram_init()
756 sdram_params->ch[channel].bw = 2; in sdram_init()
[all …]
/u-boot/include/
A DMCD_tasksInit.h16 volatile TaskTableEntry * taskTable, int channel);
22 volatile TaskTableEntry * taskTable, int channel);
27 volatile TaskTableEntry * taskTable, int channel);
33 volatile TaskTableEntry * taskTable, int channel);
37 volatile TaskTableEntry * taskTable, int channel);
41 volatile TaskTableEntry * taskTable, int channel);
A Dpwm.h26 int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
37 int (*set_enable)(struct udevice *dev, uint channel, bool enable);
46 int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
60 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
71 int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
81 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
/u-boot/arch/arm/dts/
A Dste-ab8500.dtsi58 #io-channel-cells = <1>;
61 bat_ctrl: channel@01 {
64 btemp_ball: channel@02 {
70 acc_detect1: channel@04 {
76 adc_aux1: channel@06 {
79 adc_aux2: channel@07 {
85 vbus_v: channel@09 {
94 bk_bat_v: channel@0c {
97 die_temp: channel@0d {
100 usb_id: channel@0e {
[all …]
/u-boot/arch/arm/mach-exynos/
A Ddmc_common.c97 int channel, chip; in dmc_config_mrs() local
99 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_mrs()
102 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_mrs()
138 int channel, chip; in dmc_config_prech() local
140 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_prech()
143 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_prech()
/u-boot/drivers/spmi/
A Dspmi-msm.c61 unsigned channel; in msm_spmi_write() local
69 channel = priv->channel_map[usid][pid]; in msm_spmi_write()
72 writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
76 writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA); in msm_spmi_write()
86 writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); in msm_spmi_write()
91 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
106 unsigned channel; in msm_spmi_read() local
114 channel = priv->channel_map[usid][pid]; in msm_spmi_read()
127 writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); in msm_spmi_read()
132 reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) + in msm_spmi_read()
[all …]
/u-boot/drivers/video/imx/
A Dipu.h210 void ipu_uninit_channel(ipu_channel_t channel);
212 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
219 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
222 int32_t ipu_is_channel_busy(ipu_channel_t channel);
223 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
225 int32_t ipu_enable_channel(ipu_channel_t channel);
226 int32_t ipu_disable_channel(ipu_channel_t channel);
262 void ipu_dp_dc_enable(ipu_channel_t channel);
263 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
265 void ipu_dp_uninit(ipu_channel_t channel);
[all …]
/u-boot/doc/device-tree-bindings/net/
A Dfsl,mcf-dma-fec.txt6 - rx-task: dma channel
7 - tx-task: dma channel
8 - rx-priority: dma channel
9 - tx-priority: dma channel
10 - rx-init: dma channel
11 - tx-init: dma channel

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