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Searched refs:clk_div_lv1 (Results 1 – 7 of 7) sorted by relevance

/u-boot/arch/arm/dts/
A Ds5p4418-nanopi2.dts91 clk_div_lv1 = <1>;
/u-boot/drivers/video/nexell/
A Ds5pxx18_dp.c133 nx_dpc_set_clock_divisor(module, 1, ctrl->clk_div_lv1); in dp_control_setup()
176 ctrl->clk_src_lv1, ctrl->clk_div_lv1, ctrl->clk_inv_lv1); in dp_control_setup()
A Ds5pxx18_dp_lvds.c116 nx_disp_top_clkgen_set_clock_divisor(clkid, 1, ctrl->clk_div_lv1); in lvds_setup()
A Ds5pxx18_dp_hdmi.c158 ctrl->clk_div_lv1 = 1; in hdmi_get_vsync()
A Ds5pxx18_dp_mipi.c364 ctrl->clk_div_lv1 * in mipi_enable()
/u-boot/arch/arm/mach-nexell/include/mach/
A Ddisplay.h89 int clk_div_lv1; member
/u-boot/drivers/video/
A Dnexell_display.c74 ctrl->clk_div_lv1 = ofnode_read_s32_default(node, "clk_div_lv1", 0); in nx_display_parse_dp_ctrl()
112 ctrl->clk_src_lv1, ctrl->clk_div_lv1); in nx_display_parse_dp_ctrl()

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