Searched refs:clk_enable_gpll0 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-snapdragon/
A D	clock-apq8096.c	50 clk_enable_gpll0(priv->base, &gpll0_vote_clk); in clk_init_sdc() 74 clk_enable_gpll0(priv->base, &gpll0_vote_clk); in clk_init_uart()
A D	clock-apq8016.c	63 clk_enable_gpll0(priv->base, &gpll0_vote_clk); in clk_init_sdc() 88 clk_enable_gpll0(priv->base, &gpll0_vote_clk); in clk_init_uart()
A D	clock-snapdragon.h	38 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
A D	clock-snapdragon.c	33 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) in clk_enable_gpll0() function

Completed in 4 milliseconds

Last Index update Sat Jun 03 09:59:21 CST 2023