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Searched refs:clk_period (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/mtd/nand/raw/
A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
A Dsunxi_nand.c1213 u32 clk_period) in _sunxi_nand_lookup_timing() argument
1215 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period); in _sunxi_nand_lookup_timing()
/u-boot/drivers/mmc/
A Docteontx_hsmmc.h85 uint clk_period; member
A Docteontx_hsmmc.c2428 int clk_period = 0; in octeontx_mmc_set_ios() local
2466 clk_period = octeontx_mmc_calc_clk_period(mmc); in octeontx_mmc_set_ios()
2471 emm_switch.s.clk_hi = clk_period / 2; in octeontx_mmc_set_ios()
2472 emm_switch.s.clk_lo = clk_period / 2; in octeontx_mmc_set_ios()
3335 u32 clk_period; in octeontx_mmc_init_lowlevel() local
3359 clk_period = octeontx_mmc_calc_clk_period(mmc); in octeontx_mmc_init_lowlevel()
3362 emm_switch.s.clk_lo = clk_period / 2; in octeontx_mmc_init_lowlevel()
3363 emm_switch.s.clk_hi = clk_period / 2; in octeontx_mmc_init_lowlevel()
/u-boot/drivers/memory/
A Dstm32-fmc2-ebi.c295 u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; in stm32_fmc2_ebi_ns_to_clk_period() local
297 return DIV_ROUND_UP(nb_clk_cycles, clk_period); in stm32_fmc2_ebi_ns_to_clk_period()

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