Searched refs:clk_src_lv0 (Results 1 – 7 of 7) sorted by relevance
| /u-boot/drivers/video/nexell/ |
| A D | s5pxx18_dp.c | 129 nx_dpc_set_clock_source(module, 0, ctrl->clk_src_lv0 == 3 ? in dp_control_setup()
130 6 : ctrl->clk_src_lv0); in dp_control_setup()
175 ctrl->clk_src_lv0, ctrl->clk_div_lv0, ctrl->clk_inv_lv0, in dp_control_setup()
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| A D | s5pxx18_dp_lvds.c | 113 nx_disp_top_clkgen_set_clock_source(clkid, 0, ctrl->clk_src_lv0); in lvds_setup()
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| A D | s5pxx18_dp_hdmi.c | 155 ctrl->clk_src_lv0 = 4; in hdmi_get_vsync()
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| A D | s5pxx18_dp_mipi.c | 362 nx_disp_top_clkgen_set_clock_source(clkid, 1, ctrl->clk_src_lv0); in mipi_enable()
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| /u-boot/arch/arm/dts/ |
| A D | s5p4418-nanopi2.dts | 88 clk_src_lv0 = <3>;
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| /u-boot/arch/arm/mach-nexell/include/mach/ |
| A D | display.h | 86 int clk_src_lv0; member
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| /u-boot/drivers/video/ |
| A D | nexell_display.c | 71 ctrl->clk_src_lv0 = ofnode_read_s32_default(node, "clk_src_lv0", 0); in nx_display_parse_dp_ctrl()
111 ctrl->clk_src_lv0, ctrl->clk_div_lv0, in nx_display_parse_dp_ctrl()
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