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Searched refs:clkctrl_regs (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dclock.c39 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_pclk() local
71 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_hclk() local
89 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_emiclk() local
114 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_gpmiclk() local
147 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_set_ioclk() local
180 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_ioclk() local
201 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_set_sspclk() local
245 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_get_sspclk() local
314 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_set_lcdclk() local
379 &clkctrl_regs->hw_clkctrl_pix_set); in mxs_set_lcdclk()
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A Dspl_mem_init.c145 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_mem_init_clock() local
159 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); in mxs_mem_init_clock()
163 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); in mxs_mem_init_clock()
167 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); in mxs_mem_init_clock()
174 &clkctrl_regs->hw_clkctrl_emi); in mxs_mem_init_clock()
178 &clkctrl_regs->hw_clkctrl_clkseq_clr); in mxs_mem_init_clock()
186 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_mem_setup_cpu_and_hbus() local
198 &clkctrl_regs->hw_clkctrl_clkseq_set); in mxs_mem_setup_cpu_and_hbus()
203 &clkctrl_regs->hw_clkctrl_hbus_clr); in mxs_mem_setup_cpu_and_hbus()
208 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, in mxs_mem_setup_cpu_and_hbus()
[all …]
A Dmxs.c99 struct mxs_clkctrl_regs *clkctrl_regs = in arch_cpu_init() local
110 &clkctrl_regs->hw_clkctrl_clkseq_set); in arch_cpu_init()
113 clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); in arch_cpu_init()
114 while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) in arch_cpu_init()
116 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, in arch_cpu_init()
209 struct mxs_clkctrl_regs *clkctrl_regs = in cpu_eth_init() local
213 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, in cpu_eth_init()
219 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); in cpu_eth_init()
225 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); in cpu_eth_init()
228 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); in cpu_eth_init()
A Dspl_power_init.c34 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_power_clock2xtal() local
41 &clkctrl_regs->hw_clkctrl_clkseq_set); in mxs_power_clock2xtal()
53 struct mxs_clkctrl_regs *clkctrl_regs = in mxs_power_clock2pll() local
65 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, in mxs_power_clock2pll()
73 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
/u-boot/drivers/misc/
A Dmxs_ocotp.c29 static struct mxs_clkctrl_regs *clkctrl_regs = variable
127 reg = readl(&clkctrl_regs->hw_clkctrl_hbus); in mxs_ocotp_wait_hclk_ready()
149 &clkctrl_regs->hw_clkctrl_clkseq_set); in mxs_ocotp_scale_hclk()
153 *val = readl(&clkctrl_regs->hw_clkctrl_hbus); in mxs_ocotp_scale_hclk()
167 &clkctrl_regs->hw_clkctrl_hbus_set); in mxs_ocotp_scale_hclk()
169 &clkctrl_regs->hw_clkctrl_hbus_clr); in mxs_ocotp_scale_hclk()
179 &clkctrl_regs->hw_clkctrl_clkseq_clr); in mxs_ocotp_scale_hclk()
/u-boot/board/ppcag/bg0900/
A Dbg0900.c58 struct mxs_clkctrl_regs *clkctrl_regs = in board_eth_init() local
67 &clkctrl_regs->hw_clkctrl_enet); in board_eth_init()
/u-boot/board/schulercontrol/sc_sps_1/
A Dsc_sps_1.c74 struct mxs_clkctrl_regs *clkctrl_regs = in board_eth_init() local
80 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, in board_eth_init()
/u-boot/board/freescale/mx28evk/
A Dmx28evk.c103 struct mxs_clkctrl_regs *clkctrl_regs = in board_eth_init() local
114 &clkctrl_regs->hw_clkctrl_enet); in board_eth_init()

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