Searched refs:clock (Results 1 – 25 of 1422) sorted by relevance
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| /u-boot/arch/arm/dts/ |
| A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
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| A D | am33xx-clocks.dtsi | 12 #clock-cells = <0>;
23 clock-mult = <1>;
24 clock-div = <1>;
31 clock-mult = <1>;
32 clock-div = <1>;
39 clock-mult = <1>;
40 clock-div = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
[all …]
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| A D | omap3xxx-clocks.dtsi | 12 #clock-cells = <0>;
18 #clock-cells = <0>;
25 #clock-cells = <0>;
46 clock-mult = <2>;
47 clock-div = <1>;
54 clock-mult = <2>;
55 clock-div = <1>;
62 clock-mult = <2>;
63 clock-div = <1>;
71 clock-div = <1>;
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| A D | keystone-clocks.dtsi | 17 #clock-cells = <0>;
27 #clock-cells = <0>;
30 clock-div = <1>;
31 clock-mult = <1>;
39 clock-div = <1>;
40 clock-mult = <1>;
68 clock-div = <2>;
77 clock-div = <3>;
86 clock-div = <3>;
95 clock-div = <4>;
[all …]
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| A D | dra7xx-clocks.dtsi | 12 #clock-cells = <0>;
18 #clock-cells = <0>;
24 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
111 clock-mult = <1>;
[all …]
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| A D | omap54xx-clocks.dtsi | 9 #clock-cells = <0>;
15 #clock-cells = <0>;
23 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
128 clock-mult = <1>;
129 clock-div = <8>;
202 clock-div = <1>;
[all …]
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| A D | omap36xx-omap3430es2plus-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
38 clock-mult = <1>;
39 clock-div = <2>;
54 clock-mult = <1>;
55 clock-div = <1>;
79 clock-div = <2>;
87 clock-div = <2>;
95 clock-div = <4>;
103 clock-div = <8>;
[all …]
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| A D | dm816x-clocks.dtsi | 9 #clock-cells = <1>;
25 #clock-cells = <1>;
37 #clock-cells = <1>;
48 #clock-cells = <1>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
81 #clock-cells = <0>;
90 #clock-cells = <0>;
98 #clock-cells = <0>;
[all …]
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| A D | omap44xx-clocks.dtsi | 9 #clock-cells = <0>;
15 #clock-cells = <0>;
21 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
162 clock-div = <8>;
[all …]
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| A D | keystone-k2hk-clocks.dtsi | 13 #clock-cells = <0>;
22 #clock-cells = <0>;
30 #clock-cells = <0>;
39 #clock-cells = <0>;
48 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #clock-cells = <0>;
77 #clock-cells = <0>;
87 #clock-cells = <0>;
97 #clock-cells = <0>;
[all …]
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| A D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 12 #clock-cells = <0>;
15 clock-mult = <1>;
16 clock-div = <3>;
20 #clock-cells = <0>;
23 clock-mult = <1>;
24 clock-div = <5>;
59 clock-div = <3>;
67 clock-div = <4>;
75 clock-div = <6>;
83 clock-div = <1>;
[all …]
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| A D | keystone-k2l-clocks.dtsi | 13 #clock-cells = <0>;
22 #clock-cells = <0>;
30 #clock-cells = <0>;
39 #clock-cells = <0>;
48 #clock-cells = <0>;
58 #clock-cells = <0>;
68 #clock-cells = <0>;
78 #clock-cells = <0>;
88 #clock-cells = <0>;
98 #clock-cells = <0>;
[all …]
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| A D | omap34xx-omap36xx-clocks.dtsi | 12 #clock-cells = <0>;
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
28 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #clock-cells = <0>;
80 clock-mult = <1>;
81 clock-div = <1>;
129 clock-div = <1>;
[all …]
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| A D | sama5d2.dtsi | 17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
25 clock-frequency = <0>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
107 #clock-cells = <0>;
113 #clock-cells = <0>;
119 #clock-cells = <0>;
[all …]
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| A D | am35xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
28 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #clock-cells = <0>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
69 #clock-cells = <0>;
77 #clock-cells = <0>;
83 #clock-cells = <0>;
[all …]
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| A D | keystone-k2e-clocks.dtsi | 13 #clock-cells = <0>;
21 #clock-cells = <0>;
24 clock-output-names = "papllclk";
30 #clock-cells = <0>;
39 #clock-cells = <0>;
42 clock-output-names = "usb1";
49 #clock-cells = <0>;
59 #clock-cells = <0>;
62 clock-output-names = "pcie1";
69 #clock-cells = <0>;
[all …]
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| A D | stih410-clock.dtsi | 11 #clock-cells = <0>;
18 #clock-cells = <0>;
20 clock-frequency = <0>;
38 #clock-cells = <1>;
51 #clock-cells = <0>;
63 #clock-cells = <0>;
66 clock-div = <2>;
67 clock-mult = <1>;
76 #clock-cells = <1>;
100 #clock-cells = <1>;
[all …]
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| A D | stih407-clock.dtsi | 11 #clock-cells = <0>;
17 #clock-cells = <0>;
19 clock-frequency = <0>;
35 #clock-cells = <1>;
48 #clock-cells = <0>;
62 #clock-cells = <0>;
66 clock-div = <2>;
67 clock-mult = <1>;
76 #clock-cells = <1>;
99 #clock-cells = <1>;
[all …]
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| A D | omap36xx-clocks.dtsi | 12 #clock-cells = <0>;
19 #clock-cells = <0>;
29 #clock-cells = <0>;
38 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
65 #clock-cells = <0>;
74 clock-mult = <1>;
78 clock-mult = <1>;
82 ti,clock-mult = <1>;
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| A D | exynos7420.dtsi | 11 #include <dt-bindings/clock/exynos7420-clk.h>
16 compatible = "fixed-clock";
17 clock-output-names = "fin_pll";
19 #clock-cells = <0>;
22 clock_topc: clock-controller@10570000 {
23 compatible = "samsung,exynos7-clock-topc";
26 #clock-cells = <1>;
28 clock-names = "fin_pll";
31 clock_top0: clock-controller@105d0000 {
35 #clock-cells = <1>;
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | fixed-factor-clock.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-div: fixed divider.
11 - clock-mult: fixed multiplier.
12 - clocks: parent clock.
15 - clock-output-names : From common clock binding.
18 clock {
19 compatible = "fixed-factor-clock";
21 #clock-cells = <0>;
22 clock-div = <2>;
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| /u-boot/arch/arm/mach-socfpga/ |
| A D | clock_manager_gen5.c | 347 u32 reg, clock; in cm_get_main_vco_clk_hz() local
357 return clock; in cm_get_main_vco_clk_hz()
382 return clock; in cm_get_per_vco_clk_hz()
396 return clock; in cm_get_mpu_clk_hz()
427 return clock; in cm_get_sdram_clk_hz()
462 clock = clock / (1 << reg); in cm_get_l4_sp_clk_hz()
464 return clock; in cm_get_l4_sp_clk_hz()
495 clock /= 4; in cm_get_mmc_controller_clk_hz()
496 return clock; in cm_get_mmc_controller_clk_hz()
526 return clock; in cm_get_qspi_controller_clk_hz()
[all …]
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| A D | clock_manager_s10.c | 266 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_mpu_clk_hz()
268 switch (clock) { in cm_get_mpu_clk_hz()
298 return clock; in cm_get_mpu_clk_hz()
306 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_l3_main_clk_hz()
308 switch (clock) { in cm_get_l3_main_clk_hz()
337 return clock; in cm_get_l3_main_clk_hz()
345 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_mmc_controller_clk_hz()
347 switch (clock) { in cm_get_mmc_controller_clk_hz()
374 return clock / 4; in cm_get_mmc_controller_clk_hz()
384 return clock; in cm_get_l4_sp_clk_hz()
[all …]
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| /u-boot/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ |
| A D | ucc.txt | 7 - rx-clock-name: the UCC receive clock source
8 "none": clock source is disabled
11 - tx-clock-name: the UCC transmit clock source
12 "none": clock source is disabled
16 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
20 - rx-clock : represents the UCC receive clock source.
21 0x00 : clock source is disabled;
24 - tx-clock: represents the UCC transmit clock source;
25 0x00 : clock source is disabled;
48 rx-clock = "none";
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| /u-boot/drivers/clk/at91/ |
| A D | Kconfig | 2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
13 clock, enable it and get its rate.
23 This option is used to enable the AT91 UTMI PLL clock
26 PLL is the main clock, so the main clock must select the
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