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Searched refs:clr (Results 1 – 25 of 49) sorted by relevance

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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dhardware.h9 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) argument
11 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) argument
13 #define rk_clrsetreg(addr, clr, set) \ argument
14 writel(((clr) | (set)) << 16 | (set), addr)
15 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) argument
/u-boot/arch/x86/include/asm/arch-quark/
A Dmsg_port.h111 & ~(clr)) | (set))
113 #define msg_port_clrbits(port, reg, clr) \ argument
117 #define msg_port_clrsetbits(port, reg, clr, set) \ argument
120 #define msg_port_alt_clrbits(port, reg, clr) \ argument
121 msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
124 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument
125 msg_port_generic_clrsetbits(alt, port, reg, clr, set)
127 #define msg_port_io_clrbits(port, reg, clr) \ argument
128 msg_port_generic_clrsetbits(io, port, reg, clr, 0)
131 #define msg_port_io_clrsetbits(port, reg, clr, set) \ argument
[all …]
/u-boot/include/
A Dp2sb.h110 void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set);
111 void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set);
112 void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set);
129 static inline void pcr_clrbits32(struct udevice *dev, uint offset, uint clr) in pcr_clrbits32() argument
131 return pcr_clrsetbits32(dev, offset, clr, 0); in pcr_clrbits32()
134 static inline void pcr_clrbits16(struct udevice *dev, uint offset, uint clr) in pcr_clrbits16() argument
136 return pcr_clrsetbits16(dev, offset, clr, 0); in pcr_clrbits16()
139 static inline void pcr_clrbits8(struct udevice *dev, uint offset, uint clr) in pcr_clrbits8() argument
141 return pcr_clrsetbits8(dev, offset, clr, 0); in pcr_clrbits8()
A Dvideo_console.h133 int (*set_row)(struct udevice *dev, uint row, int clr);
201 int vidconsole_set_row(struct udevice *dev, uint row, int clr);
A Dlcd_console.h16 void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr);
/u-boot/board/samsung/odroid/
A Dodroid.c166 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
178 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
181 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
251 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
274 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
294 clrsetbits_le32(&clk->src_peril0, clr, set); in board_clock_init()
307 clrsetbits_le32(&clk->div_peril0, clr, set); in board_clock_init()
326 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init()
346 clrsetbits_le32(&clk->div_fsys2, clr, set); in board_clock_init()
353 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); in board_clock_init()
[all …]
/u-boot/drivers/misc/
A Dp2sb-uclass.c132 void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits32() argument
137 data32 &= ~clr; in pcr_clrsetbits32()
142 void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits16() argument
147 data16 &= ~clr; in pcr_clrsetbits16()
152 void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set) in pcr_clrsetbits8() argument
157 data8 &= ~clr; in pcr_clrsetbits8()
A Dsmsc_sio1007.c24 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) in sio1007_clrsetbits() argument
26 sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); in sio1007_clrsetbits()
/u-boot/drivers/net/
A Dpic32_eth.c90 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init()
148 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link()
157 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link()
203 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init()
255 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset()
258 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset()
259 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset()
262 writel(0x00ff, &ectl_p->rxfc.clr); in pic32_ctrl_reset()
369 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
380 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
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/u-boot/drivers/gpio/
A Dpic32_gpio.c59 writel(mask, &priv->regs->port.clr); in pic32_gpio_set_value()
83 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_input()
95 writel(mask, &priv->regs->ansel.clr); in pic32_gpio_direction_output()
96 writel(mask, &priv->regs->tris.clr); in pic32_gpio_direction_output()
/u-boot/common/
A Dlcd_console_rotation.c31 static inline void console_setrow90(struct console_t *pcons, u32 row, int clr) in console_setrow90() argument
40 *dst-- = clr; in console_setrow90()
86 static inline void console_setrow180(struct console_t *pcons, u32 row, int clr) in console_setrow180() argument
94 *dst++ = clr; in console_setrow180()
133 static inline void console_setrow270(struct console_t *pcons, u32 row, int clr) in console_setrow270() argument
141 *dst++ = clr; in console_setrow270()
A Dlcd_console.c66 static inline void console_setrow0(struct console_t *pcons, u32 row, int clr) in console_setrow0() argument
74 *dst++ = clr; in console_setrow0()
/u-boot/drivers/video/
A Dconsole_rotate.c14 static int console_set_row_1(struct udevice *dev, uint row, int clr) in console_set_row_1() argument
32 *dst++ = clr; in console_set_row_1()
40 *dst++ = clr; in console_set_row_1()
48 *dst++ = clr; in console_set_row_1()
157 static int console_set_row_2(struct udevice *dev, uint row, int clr) in console_set_row_2() argument
173 *dst++ = clr; in console_set_row_2()
182 *dst++ = clr; in console_set_row_2()
191 *dst++ = clr; in console_set_row_2()
310 *dst++ = clr; in console_set_row_3()
318 *dst++ = clr; in console_set_row_3()
[all …]
A Dconsole_normal.c16 static int console_normal_set_row(struct udevice *dev, uint row, int clr) in console_normal_set_row() argument
31 *dst++ = clr; in console_normal_set_row()
40 *dst++ = clr; in console_normal_set_row()
49 *dst++ = clr; in console_normal_set_row()
A Dconsole_truetype.c126 static int console_truetype_set_row(struct udevice *dev, uint row, int clr) in console_truetype_set_row() argument
141 *dst++ = clr; in console_truetype_set_row()
151 *dst++ = clr; in console_truetype_set_row()
161 *dst++ = clr; in console_truetype_set_row()
355 int xend, int yend, int clr) in console_truetype_erase() argument
372 *dst++ = clr; in console_truetype_erase()
381 *dst++ = clr; in console_truetype_erase()
390 *dst++ = clr; in console_truetype_erase()
/u-boot/drivers/spi/
A Dbcm63xx_hsspi.c145 uint32_t clr, set; in bcm63xx_hsspi_activate_cs() local
156 clr = SPI_PFL_SIG_LAUNCHRIS_MASK | in bcm63xx_hsspi_activate_cs()
170 clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); in bcm63xx_hsspi_activate_cs()
174 clr = 0; in bcm63xx_hsspi_activate_cs()
178 clr |= BIT(plat->cs); in bcm63xx_hsspi_activate_cs()
184 clr |= BIT(!plat->cs); in bcm63xx_hsspi_activate_cs()
188 clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()
/u-boot/arch/x86/cpu/
A Dpci.c58 int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set, in pci_x86_clrset_config() argument
67 value &= ~clr; in pci_x86_clrset_config()
/u-boot/arch/x86/include/asm/
A Dpci.h60 int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set,
/u-boot/arch/mips/mach-pic32/include/mach/
A Dpic32.h61 u32 clr; member
/u-boot/drivers/clk/mtmips/
A Dclk-mt7620.c65 static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set) in mt7620_clkcfg1_rmw() argument
76 val &= ~clr; in mt7620_clkcfg1_rmw()
/u-boot/drivers/sound/
A Drockchip_i2s.c27 u32 clr; /* I2S_CLR, 0x20 */ member
101 writel(0, &regs->clr); in i2s_send_data()
/u-boot/drivers/power/regulator/
A Dtps65910_regulator.c269 uint clr, set; in tps65910_set_enable() local
277 clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_ON; in tps65910_set_enable()
280 clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_OFF; in tps65910_set_enable()
283 return pmic_clrsetbits(dev->parent, reg, clr, set); in tps65910_set_enable()
/u-boot/drivers/mmc/
A Dftsdc010_mci.c90 &regs->clr); in ftsdc010_send_cmd()
97 writel(FTSDC010_STATUS_CMD_SEND, &regs->clr); in ftsdc010_send_cmd()
106 writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr); in ftsdc010_send_cmd()
168 writel(st & mask, &regs->clr); in ftsdc010_wait()
211 | FTSDC010_STATUS_FIFO_ORUN, &regs->clr); in ftsdc010_request()
/u-boot/drivers/phy/
A Dmt76x8-usb-phy.c91 static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set) in phy_rmw32() argument
93 clrsetbits_32(phy->base + reg, clr, set); in phy_rmw32()
/u-boot/drivers/power/pmic/
A Dpmic-uclass.c168 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) in pmic_clrsetbits() argument
183 val = (val & ~clr) | set; in pmic_clrsetbits()

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