Searched refs:clrsetbits_32 (Results 1 – 12 of 12) sorted by relevance
| /u-boot/arch/mips/mach-mtmips/mt7620/ |
| A D | serial.c | 17 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, in board_debug_uart_init()
32 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, in mtmips_spl_serial_init()
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| A D | sysc.c | 104 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, in mt7620_sysc_ioctl()
117 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, in mt7620_sysc_ioctl()
130 clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, in mt7620_sysc_ioctl()
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| A D | init.c | 38 clrsetbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPU_CLK_AUX1, CPU_CLK_AUX0); in cpu_pll_init()
47 clrsetbits_32(sysc + SYSCTL_CPLL_CFG0_REG, PLL_MULT_RATIO_M | in cpu_pll_init()
62 clrsetbits_32(sysc + SYSCTL_CPU_SYS_CLKCFG_REG, in cpu_pll_init()
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| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | serial.c | 25 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, in mtmips_spl_serial_init()
29 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, in mtmips_spl_serial_init()
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| /u-boot/drivers/pinctrl/mtmips/ |
| A D | pinctrl-mt7628.c | 459 clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit); in mt7628_set_drv_strength()
460 clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit); in mt7628_set_drv_strength()
500 clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG, in mt7628_pinconf_set()
514 clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG, in mt7628_pinconf_set()
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| /u-boot/drivers/spi/ |
| A D | bcm63xx_hsspi.c | 170 clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); in bcm63xx_hsspi_activate_cs()
188 clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()
194 clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, in bcm63xx_hsspi_deactivate_cs()
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| /u-boot/drivers/serial/ |
| A D | serial_bcm6345.c | 124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
151 clrsetbits_32(base + UART_FIFO_CFG_REG, in bcm6345_serial_init()
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| /u-boot/arch/mips/mach-mtmips/ |
| A D | ddr_init.c | 96 clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M, in mc_ddr_init()
217 clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M, in mc_sdr_init()
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| /u-boot/drivers/led/ |
| A D | led_bcm6858.c | 179 clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits); in bcm6858_led_probe()
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| /u-boot/drivers/phy/ |
| A D | mt76x8-usb-phy.c | 93 clrsetbits_32(phy->base + reg, clr, set); in phy_rmw32()
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| /u-boot/drivers/net/ |
| A D | bcmgenet.c | 457 clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, in bcmgenet_adjust_link()
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| /u-boot/arch/arm/include/asm/ |
| A D | io.h | 220 #define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set) macro
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