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Searched refs:con (Results 1 – 25 of 34) sorted by relevance

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/u-boot/test/dm/
A Dvideo.c119 struct udevice *dev, *con; in dm_test_video_text() local
154 struct udevice *dev, *con; in dm_test_video_chars() local
172 struct udevice *dev, *con; in dm_test_video_ansi() local
179 video_clear(con->parent); in dm_test_video_ansi()
180 video_sync(con->parent, false); in dm_test_video_ansi()
214 struct udevice *dev, *con; in check_vidconsole_output() local
235 vidconsole_put_char(con, '\n'); in check_vidconsole_output()
241 vidconsole_put_char(con, '\n'); in check_vidconsole_output()
341 struct udevice *dev, *con; in dm_test_video_truetype() local
357 struct udevice *dev, *con; in dm_test_video_truetype_scroll() local
[all …]
/u-boot/drivers/clk/rockchip/
A Dclk_px30.c265 u32 con, shift, mask; in rkclk_pll_get_rate() local
267 con = readl(mode); in rkclk_pll_get_rate()
292 u32 div, con; in px30_i2c_get_clk() local
483 u32 div, con; in px30_nandc_get_clk() local
515 u32 div, con, con_id; in px30_mmc_get_clk() local
587 u32 div, con; in px30_pwm_get_clk() local
640 u32 div, con; in px30_saradc_get_clk() local
666 u32 div, con; in px30_tsadc_get_clk() local
692 u32 div, con; in px30_spi_get_clk() local
1029 u32 con; in px30_i2s1_mclk_get_clk() local
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A Dclk_rk3308.c132 u32 div, con, con_id; in rk3308_i2c_get_clk() local
242 u32 div, con, con_id; in rk3308_mmc_get_clk() local
314 u32 div, con; in rk3308_saradc_get_clk() local
316 con = readl(&cru->clksel_con[34]); in rk3308_saradc_get_clk()
342 u32 div, con; in rk3308_tsadc_get_clk() local
344 con = readl(&cru->clksel_con[33]); in rk3308_tsadc_get_clk()
370 u32 div, con, con_id; in rk3308_spi_get_clk() local
429 u32 div, con; in rk3308_pwm_get_clk() local
460 con = readl(&cru->clksel_con[8]); in rk3308_vop_get_clk()
463 div = con & DCLK_VOP_DIV_MASK; in rk3308_vop_get_clk()
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A Dclk_rk3128.c246 u32 con; in rkclk_pll_get_rate() local
260 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
269 con = readl(&pll->con0); in rkclk_pll_get_rate()
272 con = readl(&pll->con1); in rkclk_pll_get_rate()
287 u32 con; in rockchip_mmc_get_clk() local
352 u32 div, con; in rk3128_peri_get_pclk() local
361 div = con >> 12 & 0x3; in rk3128_peri_get_pclk()
461 u32 div, con, parent; in rk3128_vop_get_rate() local
466 div = con & 0x1f; in rk3128_vop_get_rate()
471 div = (con >> 8) & 0x1f; in rk3128_vop_get_rate()
[all …]
A Dclk_rk3036.c178 uint32_t con; in rkclk_pll_get_rate() local
192 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
196 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
202 con = readl(&pll->con0); in rkclk_pll_get_rate()
205 con = readl(&pll->con1); in rkclk_pll_get_rate()
220 u32 con; in rockchip_mmc_get_clk() local
225 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
226 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
227 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
231 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
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A Dclk_rk3288.c548 uint32_t con; in rkclk_pll_get_rate() local
557 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
564 con = readl(&pll->con0); in rkclk_pll_get_rate()
567 con = readl(&pll->con1); in rkclk_pll_get_rate()
582 u32 con; in rockchip_mmc_get_clk() local
587 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
593 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
599 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
665 u32 con; in rockchip_spi_get_clk() local
669 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
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A Dclk_rk322x.c180 uint32_t con; in rkclk_pll_get_rate() local
194 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
198 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
204 con = readl(&pll->con0); in rkclk_pll_get_rate()
207 con = readl(&pll->con1); in rkclk_pll_get_rate()
221 u32 con; in rockchip_mmc_get_clk() local
227 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
228 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
229 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
234 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
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A Dclk_rk3188.c234 uint32_t con; in rkclk_pll_get_rate() local
243 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
250 con = readl(&pll->con0); in rkclk_pll_get_rate()
253 con = readl(&pll->con1); in rkclk_pll_get_rate()
267 u32 con; in rockchip_mmc_get_clk() local
272 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
277 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
282 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
332 u32 con; in rockchip_spi_get_clk() local
336 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
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A Dclk_pll.c255 u32 con = 0, shift, mask; in rk3036_pll_get_rate() local
258 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
262 switch ((con & mask) >> shift) { in rk3036_pll_get_rate()
267 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
268 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> in rk3036_pll_get_rate()
270 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> in rk3036_pll_get_rate()
272 con = readl(base + pll->con_offset + 0x4); in rk3036_pll_get_rate()
275 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> in rk3036_pll_get_rate()
277 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> in rk3036_pll_get_rate()
279 con = readl(base + pll->con_offset + 0x8); in rk3036_pll_get_rate()
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A Dclk_rk3328.c338 u32 div, con; in rk3328_i2c_get_clk() local
342 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
346 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
350 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
354 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
425 u32 con = readl(&cru->clksel_con[27]); in rk3328_gmac2io_set_clk() local
449 u32 div, con, con_id; in rk3328_mmc_get_clk() local
463 con = readl(&cru->clksel_con[con_id]); in rk3328_mmc_get_clk()
466 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT in rk3328_mmc_get_clk()
514 u32 div, con; in rk3328_pwm_get_clk() local
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A Dclk_rv1108.c151 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk() local
155 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) in rv1108_mac_set_clk()
176 u32 con = readl(&cru->clksel_con[27]); in rv1108_sfc_set_clk() local
421 u32 div, con; in rv1108_i2c_get_clk() local
425 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
430 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
435 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
440 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
495 u32 div, con; in rv1108_mmc_get_clk() local
498 con = readl(&cru->clksel_con[26]); in rv1108_mmc_get_clk()
[all …]
A Dclk_rk3368.c70 uint32_t con; in rkclk_pll_get_rate() local
73 con = readl(&pll->con3); in rkclk_pll_get_rate()
79 con = readl(&pll->con0); in rkclk_pll_get_rate()
80 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; in rkclk_pll_get_rate()
81 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; in rkclk_pll_get_rate()
82 con = readl(&pll->con1); in rkclk_pll_get_rate()
83 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; in rkclk_pll_get_rate()
164 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
181 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
182 switch (con & MMC_PLL_SEL_MASK) { in rk3368_mmc_get_clk()
[all …]
A Dclk_rk3399.c521 u32 div, con; in rk3399_i2c_get_clk() local
526 div = I2C_CLK_DIV_VALUE(con, 1); in rk3399_i2c_get_clk()
530 div = I2C_CLK_DIV_VALUE(con, 2); in rk3399_i2c_get_clk()
534 div = I2C_CLK_DIV_VALUE(con, 3); in rk3399_i2c_get_clk()
538 div = I2C_CLK_DIV_VALUE(con, 5); in rk3399_i2c_get_clk()
542 div = I2C_CLK_DIV_VALUE(con, 6); in rk3399_i2c_get_clk()
546 div = I2C_CLK_DIV_VALUE(con, 7); in rk3399_i2c_get_clk()
728 u32 div, con; in rk3399_mmc_get_clk() local
1464 u32 div, con; in rk3399_i2c_get_pmuclk() local
1469 div = I2C_CLK_DIV_VALUE(con, 0); in rk3399_i2c_get_pmuclk()
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/u-boot/board/gdsys/mpc8308/
A Dgazerbeam.c50 int con = 0; in board_early_init_r() local
62 sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); in board_early_init_r()
73 if (mc == 2 || con == VAR_CON) { in board_early_init_r()
79 if (con == VAR_CON) { in board_early_init_r()
93 int con = 0; in checksysinfo() local
99 sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); in checksysinfo()
103 printf("%s", con == VAR_CON ? "CON" : "CPU"); in checksysinfo()
/u-boot/board/atmel/common/
A Dvideo_display.c31 struct udevice *dev, *con; in at91_video_show_board_info() local
66 ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); in at91_video_show_board_info()
70 priv = dev_get_uclass_priv(con); in at91_video_show_board_info()
71 vidconsole_position_cursor(con, 0, (logo_info.logo_height + in at91_video_show_board_info()
74 vidconsole_put_char(con, *s); in at91_video_show_board_info()
/u-boot/drivers/sound/
A Dsamsung-i2s.c63 unsigned int con = readl(&i2s_reg->con); in i2s_txctrl() local
67 con |= CON_ACTIVE; in i2s_txctrl()
68 con &= ~CON_TXCH_PAUSE; in i2s_txctrl()
70 con |= CON_TXCH_PAUSE; in i2s_txctrl()
71 con &= ~CON_ACTIVE; in i2s_txctrl()
75 writel(con, &i2s_reg->con); in i2s_txctrl()
282 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { in i2s_transfer_tx_data()
335 writel(CON_RESET, &i2s_reg->con); in i2s_tx_init()
/u-boot/drivers/sysinfo/
A Dgazerbeam.c65 int mc4, mc2, sc, mc2_sc, con; in _read_sysinfo_variant_data() local
117 con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); in _read_sysinfo_variant_data()
118 if (con < 0) { in _read_sysinfo_variant_data()
120 dev->name, con); in _read_sysinfo_variant_data()
121 return con; in _read_sysinfo_variant_data()
124 priv->variant = con ? VAR_CON : VAR_CPU; in _read_sysinfo_variant_data()
/u-boot/board/kosagi/novena/
A Dnovena.c131 struct udevice *con; in board_late_init() local
137 ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); in board_late_init()
142 vidconsole_position_cursor(con, 0, 0); in board_late_init()
143 vidconsole_put_string(con, buf); in board_late_init()
/u-boot/drivers/i2c/
A Drk_i2c.c88 debug("i2c_con: 0x%08x\n", readl(&regs->con)); in rk_i2c_show_regs()
112 writel(I2C_CON_EN | I2C_CON_START, &regs->con); in rk_i2c_send_start_bit()
140 writel(I2C_CON_EN | I2C_CON_STOP, &regs->con); in rk_i2c_send_stop_bit()
162 writel(0, &i2c->regs->con); in rk_i2c_disable()
174 uint con = 0; in rk_i2c_read() local
199 con = I2C_CON_EN; in rk_i2c_read()
206 con = I2C_CON_EN | I2C_CON_LASTACK; in rk_i2c_read()
215 con |= I2C_CON_MOD(I2C_MODE_RX); in rk_i2c_read()
217 con |= I2C_CON_MOD(I2C_MODE_TRX); in rk_i2c_read()
219 writel(con, &regs->con); in rk_i2c_read()
[all …]
/u-boot/lib/efi/
A Defi.c40 struct efi_simple_text_output_protocol *con = priv->sys_table->con_out; in efi_putc() local
45 con->output_string(con, ucode); in efi_putc()
/u-boot/lib/efi_loader/
A Defi_console.c179 if (con->cursor_column) in efi_cout_output_string()
180 con->cursor_column--; in efi_cout_output_string()
183 con->cursor_column = 0; in efi_cout_output_string()
184 con->cursor_row++; in efi_cout_output_string()
187 con->cursor_column = 0; in efi_cout_output_string()
198 con->cursor_column++; in efi_cout_output_string()
201 if (con->cursor_column >= mode->columns) { in efi_cout_output_string()
202 con->cursor_column = 0; in efi_cout_output_string()
203 con->cursor_row++; in efi_cout_output_string()
209 if (con->cursor_row >= mode->rows && con->cursor_row) in efi_cout_output_string()
[all …]
/u-boot/drivers/mmc/
A Domap_hsmmc.c288 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
309 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
380 writel(readl(&mmc_base->con) | DDR, &mmc_base->con); in omap_hsmmc_set_timing()
382 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); in omap_hsmmc_set_timing()
446 u32 con; in omap_hsmmc_wait_dat0() local
452 con = readl(&mmc_base->con); in omap_hsmmc_wait_dat0()
453 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con); in omap_hsmmc_wait_dat0()
464 writel(con, &mmc_base->con); in omap_hsmmc_wait_dat0()
1395 &mmc_base->con);
1400 &mmc_base->con);
[all …]
/u-boot/drivers/power/
A Dexynos-tmu.c268 unsigned te_code, con; in tmu_setup_parameters() local
319 con = readl(&reg->tmu_control); in tmu_setup_parameters()
320 con |= THERM_TRIP_EN | CORE_EN | (info->tmu_mux << 20); in tmu_setup_parameters()
322 writel(con, &reg->tmu_control); in tmu_setup_parameters()
/u-boot/include/
A Di2s.h70 unsigned int con; /* base + 0 , Control register */ member
/u-boot/arch/arm/include/asm/arch-rockchip/
A Di2c.h11 u32 con; member

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