| /u-boot/drivers/adc/ |
| A D | exynos-adc.c | 49 cfg = readl(®s->con1); in exynos_adc_start_channel()
50 writel(cfg | ADC_V2_CON1_STC_EN, ®s->con1); in exynos_adc_start_channel()
64 cfg = readl(®s->con1); in exynos_adc_stop()
67 writel(cfg, ®s->con1); in exynos_adc_stop()
87 writel(ADC_V2_CON1_SOFT_RESET, ®s->con1); in exynos_adc_probe()
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| /u-boot/drivers/clk/exynos/ |
| A D | clk-pll.c | 19 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
21 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
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| A D | clk-pll.h | 8 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
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| /u-boot/drivers/net/ |
| A D | pic32_eth.c | 77 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
252 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
276 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
303 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
325 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
362 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
369 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
380 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
420 writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set); in pic32_eth_send()
435 if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) { in pic32_eth_send()
[all …]
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| A D | pic32_eth.h | 15 struct pic32_reg_atomic con1; /* 0x00 */ member
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| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | adc.h | 58 unsigned int con1; member
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk322x.c | 64 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
66 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
71 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
76 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
79 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
207 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| A D | clk_rk3128.c | 59 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
61 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
66 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
71 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
74 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
272 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| A D | clk_rk3036.c | 67 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
72 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
77 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
205 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| A D | clk_rv1108.c | 100 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
127 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
136 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
138 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
139 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
140 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
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| A D | clk_rk3368.c | 82 con = readl(&pll->con1); in rkclk_pll_get_rate()
111 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
124 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
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| A D | clk_px30.c | 237 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
239 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
244 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
249 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
252 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) in rkclk_set_pll()
279 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| A D | clk_rk3188.c | 111 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
253 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| A D | clk_rk3288.c | 171 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
567 con = readl(&pll->con1); in rkclk_pll_get_rate()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3188.h | 36 u32 con1; member
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| A D | cru_rk3368.h | 27 unsigned int con1; member
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| A D | cru_rk3036.h | 33 unsigned int con1; member
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| A D | cru_rk3128.h | 38 unsigned int con1; member
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| A D | cru_rk322x.h | 34 unsigned int con1; member
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| A D | cru_rk3288.h | 37 u32 con1; member
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| A D | cru_rv1108.h | 30 unsigned int con1; member
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| A D | cru_px30.h | 44 unsigned int con1; member
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| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| A D | sdram_rk3036.c | 337 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
343 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
348 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()
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| /u-boot/arch/arm/include/asm/arch-rk3308/ |
| A D | cru_rk3308.h | 56 unsigned int con1; member
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| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_px30.c | 186 &dram->cru->pll[1].con1); in rkclk_set_dpll()
190 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
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