Searched refs:con3 (Results 1 – 12 of 12) sorted by relevance
| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rv1108.c | 91 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
95 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); in rkclk_set_pll()
97 rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
108 rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
117 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
127 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
132 con3 = readl(&pll->con3); in rkclk_pll_get_rate()
134 if (con3 & WORK_MODE_MASK) { in rkclk_pll_get_rate()
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| A D | clk_rk3368.c | 73 con = readl(&pll->con3); in rkclk_pll_get_rate()
105 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
121 rk_clrreg(&pll->con3, PLL_RESET_MASK); in rkclk_set_pll()
127 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
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| A D | clk_rk3188.c | 106 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
119 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
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| A D | clk_rk3288.c | 167 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
177 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3188.h | 38 u32 con3; member
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| A D | cru_rk3368.h | 29 unsigned int con3; member
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| A D | cru_rk3036.h | 35 unsigned int con3; member
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| A D | cru_rk3128.h | 40 unsigned int con3; member
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| A D | cru_rk3288.h | 39 u32 con3; member
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| A D | cru_rv1108.h | 32 unsigned int con3; member
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| A D | cru_px30.h | 46 unsigned int con3; member
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| /u-boot/arch/arm/include/asm/arch-rk3308/ |
| A D | cru_rk3308.h | 58 unsigned int con3; member
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