Searched refs:config_2 (Results 1 – 12 of 12) sorted by relevance
| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
115 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
147 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
179 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
211 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
243 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
275 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
307 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 54 .cs[0].config_2 = 0,
56 .cs[1].config_2 = 0,
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| /u-boot/drivers/ddr/fsl/ |
| A D | arm_ddr_gen3.c | 74 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
79 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
84 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
89 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 106 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
111 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
116 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
121 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
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| A D | fsl_ddr_gen4.c | 133 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
143 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
153 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
163 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
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| A D | interactive.c | 616 CFG_REGS_CS(0, config_2), in print_fsl_memctl_config_regs()
620 CFG_REGS_CS(1, config_2), in print_fsl_memctl_config_regs()
625 CFG_REGS_CS(2, config_2), in print_fsl_memctl_config_regs()
630 CFG_REGS_CS(3, config_2), in print_fsl_memctl_config_regs()
707 CFG_REGS_CS(0, config_2), in fsl_ddr_regs_edit()
711 CFG_REGS_CS(1, config_2), in fsl_ddr_regs_edit()
716 CFG_REGS_CS(2, config_2), in fsl_ddr_regs_edit()
721 CFG_REGS_CS(3, config_2), in fsl_ddr_regs_edit()
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| A D | ctrl_regs.c | 255 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
256 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
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| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 85 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, in fixed_sdram()
89 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, in fixed_sdram()
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 69 ddr_cfg_regs.cs[1].config_2 = 0; in fsl_initdram()
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| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 25 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
52 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 214 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, in fixed_sdram()
218 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_ddr_sdram.h | 246 unsigned int config_2; member
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