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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dmp.c80 u32 cores, cpu_up_mask = 1; in fsl_layerscape_wake_seconday_cores() local
127 cores = cpu_mask(); in fsl_layerscape_wake_seconday_cores()
148 rst->brrl = cores; in fsl_layerscape_wake_seconday_cores()
180 gur_out32(&gur->brrl, cores); in fsl_layerscape_wake_seconday_cores()
184 scfg_out32(&scfg->corebcr, cores); in fsl_layerscape_wake_seconday_cores()
202 if (hweight32(cpu_up_mask) == hweight32(cores)) in fsl_layerscape_wake_seconday_cores()
208 cores ^ cpu_up_mask); in fsl_layerscape_wake_seconday_cores()
211 printf("CPU: %d cores online\n", hweight32(cores)); in fsl_layerscape_wake_seconday_cores()
250 u32 cores = cpu_pos_mask(); in core_to_pos() local
255 } else if (nr >= hweight32(cores)) { in core_to_pos()
/u-boot/drivers/remoteproc/
A Dti_k3_r5f_rproc.c119 struct k3_r5f_core *cores[NR_CORES]; member
124 return core == core->cluster->cores[0]; in is_primary_core()
187 reset_assert(&cluster->cores[c]->reset); in k3_r5f_lockstep_release()
269 if (!core->cluster->cores[0]->in_use) { in k3_r5f_core_sanity_check()
403 ret = k3_r5f_core_run(cluster->cores[c]); in k3_r5f_start()
426 k3_r5f_core_halt(cluster->cores[c]); in k3_r5f_start()
507 k3_r5f_core_halt(cluster->cores[c]); in k3_r5f_stop()
765 if (core == cluster->cores[0]) { in k3_r5f_core_adjust_tcm_sizes()
796 if (!cluster->cores[0]) in k3_r5f_probe()
797 cluster->cores[0] = core; in k3_r5f_probe()
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/u-boot/doc/
A DREADME.mpc85xx-spin-table6 __secondary_start_page. For other cores to use the spin table, the booting
12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
A DREADME.Heterogeneous-SoCs5 configuration and frequencies of all PowerPC cores and devices
7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
19 Code added in this file to print the DSP cores and other device's(CPRI,
25 required cores and devices from RCW and System frequency
29 Added API to get the number of SC cores in running system and Their BIT
44 Global structure updated for dsp cores and other components
73 DSP cores and other device's components have been added in this structure.
A DREADME.srio-pcie-boot-corenet22 the boot location to SRIO or PCIE, and holdoff all the cores.
37 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
44 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
70 h) Since all cores of slave in holdoff, slave should be powered on before
85 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
A DREADME.socfpga28 projects must have the IP cores updated as shown below.
42 Then (if necessary) update the IP cores in the project, generate HDL code, and
46 $ qsys-generate soc_system.qsys --upgrade-ip-cores
/u-boot/drivers/axi/
A DKconfig7 communication with IP cores in Xilinx FPGAs).
23 IP cores in the FPGA (e.g. video transmitter cores).
/u-boot/drivers/cpu/
A DKconfig15 Support CPU cores for SoCs of the MPC83xx series.
21 Support CPU cores for RISC-V architecture.
/u-boot/doc/device-tree-bindings/remoteproc/
A Dti,k3-r5f-rproc.txt7 or in a Split mode providing two individual compute cores for doubling
15 cores. Each node has a number of required or optional properties that enable
41 - ti,cluster-mode: Configuration Mode for the Dual R5F cores within the R5F
59 "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
60 "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
61 "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
74 cores.
89 The following properties are optional properties for each of the R5F cores:
A Dti,k3-dsp-rproc.txt10 a dedicated local power/sleep controller etc. The DSP processor cores in the
45 cores.
/u-boot/arch/x86/cpu/intel_common/
A Dcpu.c300 int cores = 1; in cpu_get_cores_per_package() local
306 cores = result.ebx & 0xff; in cpu_get_cores_per_package()
308 return cores; in cpu_get_cores_per_package()
/u-boot/board/freescale/ls1028a/
A DREADME31 Two Arm Cortex- A72 processor cores:
34 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
36 - Arranged as a single cluster of two cores sharing a single 1 MB L2
110 Two Arm Cortex- A72 processor cores:
113 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
115 - Arranged as a single cluster of two cores sharing a single 1 MB L2
/u-boot/arch/arm/dts/
A Dsocfpga_arria5.dtsi7 /* First 4KB has trampoline code for secondary cores. */
A Dsocfpga_cyclone5.dtsi7 /* First 4KB has trampoline code for secondary cores. */
A Dvexpress-v2p-ca15_a7.dts360 /* Total current for the two A15 cores */
367 /* Total current for the three A7 cores */
381 /* Total power for the two A15 cores */
388 /* Total power for the three A7 cores */
395 /* Total energy for the two A15 cores */
402 /* Total energy for the three A7 cores */
A Dfsl-imx8-ca35.dtsi14 /* We have 1 clusters having 4 Cortex-A35 cores */
/u-boot/arch/mips/mach-octeon/
A Dcvmx-coremask.c181 u64 cores; in octeon_get_available_coremask() local
206 cores = __builtin_popcountll(ciu_fuse); in octeon_get_available_coremask()
208 cvmx_coremask_set_cores(pcm, 0, cores); in octeon_get_available_coremask()
/u-boot/doc/device-tree-bindings/axi/
A Dgdsys,ihs_axi.txt4 the connected devices (usually IP cores) can be controlled via software.
/u-boot/arch/arm/cpu/armv7/ls102xa/
A DKconfig40 cores, count the reserved ports. This will allocate enough memory
41 in spin table to properly handle all cores.
/u-boot/arch/arm/cpu/armv8/
A DKconfig18 bool "Enable data coherency with other cores in cluster"
23 For A53, it enables data coherency with other cores in the
26 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
153 of CPU cores, platforms with asymmetric clusters don't apply here.
/u-boot/doc/board/freescale/
A Db4860qds.rst12 StarCore and Power Architecture® cores. It targets the broadband wireless
33 e6500 cores, SC3900 FVP cores, memories and external interfaces.
43 buffer management, and allocation tasks from the cores
125 1. Less e6500 cores: 1 cluster with 2 e6500 cores
126 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.soc17 processor cores with datapath acceleration optimized for L2/3 packet
55 architecture combining eight ARM A53 processor cores
65 - Cores are in 2 cluster of 4-cores each
87 processor cores with high-performance data path acceleration logic and network
173 processor cores with datapath acceleration optimized for L2/3 packet
214 processor cores with high-performance data path acceleration logic and network
282 cores with advanced, high-performance datapath acceleration and
337 The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with
341 The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
387 combining sixteen ARM A72 processor cores with advanced, high-performance
/u-boot/doc/arch/
A Darc.rst10 More information on ARC cores avaialble here:
/u-boot/arch/arc/
A DKconfig18 The original ARC ISA of ARC600/700 cores
23 ISA for the Next Generation ARC-HS cores
/u-boot/arch/arm/mach-rockchip/rk3368/
A DKconfig14 - 8x Cortex-A53 (in 2 clusters of 4 cores each)

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