Searched refs:cpll (Results 1 – 3 of 3) sorted by relevance
| /u-boot/arch/m68k/cpu/mcf52x2/ |
| A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3368.c | 137 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
153 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
157 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
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| /u-boot/arch/arm/dts/ |
| A D | rk3328.dtsi | 776 * We need set cpll child clk div first,
777 * and then set the cpll frequency.
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