| /u-boot/include/faraday/ |
| A D | ftpmu010.h | 142 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) argument
143 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) argument
147 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) argument
148 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) argument
172 void ftpmu010_sdram_clk_disable(unsigned int cr0);
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| /u-boot/arch/x86/cpu/ |
| A D | start16.S | 27 movl %cr0, %eax
29 movl %eax, %cr0
37 movl %cr0, %eax
39 movl %eax, %cr0
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| A D | call32.S | 41 movl %cr0, %eax
43 movl %eax, %cr0
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| A D | sipi_vector.S | 51 movl %cr0, %eax
55 movl %eax, %cr0
185 mov %cr0, %eax
187 mov %eax, %cr0
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| A D | wakeup.S | 49 movl %cr0, %eax
51 movl %eax, %cr0
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| A D | start.S | 49 movl %cr0, %eax
51 movl %eax, %cr0
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| /u-boot/arch/x86/cpu/intel_common/ |
| A D | car.S | 102 movl %cr0, %eax
105 movl %eax, %cr0
129 movl %cr0, %eax
131 movl %eax, %cr0
161 movl %cr0, %eax
163 movl %eax, %cr0
179 movl %cr0, %eax
181 movl %eax, %cr0
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| A D | car2.S | 158 mov %cr0, %eax
161 mov %eax, %cr0
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| /u-boot/arch/x86/cpu/i386/ |
| A D | cpu.c | 498 unsigned long cr0; in x86_enable_caches() local
500 cr0 = read_cr0(); in x86_enable_caches()
501 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); in x86_enable_caches()
502 write_cr0(cr0); in x86_enable_caches()
509 unsigned long cr0; in x86_disable_caches() local
511 cr0 = read_cr0(); in x86_disable_caches()
512 cr0 |= X86_CR0_NW | X86_CR0_CD; in x86_disable_caches()
514 write_cr0(cr0); in x86_disable_caches()
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| A D | call64.S | 71 movl %eax, %cr0
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| A D | interrupt.c | 89 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; in dump_regs() local
132 cr0 = read_cr0(); in dump_regs()
138 cr0, cr2, cr3, cr4); in dump_regs()
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| /u-boot/drivers/power/ |
| A D | ftpmu010.c | 68 void ftpmu010_sdram_clk_disable(unsigned int cr0) in ftpmu010_sdram_clk_disable() argument
74 pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); in ftpmu010_sdram_clk_disable()
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| /u-boot/arch/x86/lib/ |
| A D | bios_asm.S | 65 movl %cr0, %eax
67 movl %eax, %cr0
113 movl %cr0, %eax
115 movl %eax, %cr0
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| /u-boot/drivers/spi/ |
| A D | designware_spi.c | 488 u32 cr0 = 0; in dw_spi_xfer() local
513 cr0 = priv->update_cr0(priv); in dw_spi_xfer()
525 dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, in dw_spi_xfer()
528 if (dw_read(priv, DW_SPI_CTRLR0) != cr0) in dw_spi_xfer()
529 dw_write(priv, DW_SPI_CTRLR0, cr0); in dw_spi_xfer()
577 u32 cr0; in dw_spi_exec_op() local
584 cr0 = priv->update_cr0(priv); in dw_spi_exec_op()
585 dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in, in dw_spi_exec_op()
589 dw_write(priv, DW_SPI_CTRLR0, cr0); in dw_spi_exec_op()
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| A D | pl022_spi.c | 215 u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr, in pl022_spi_set_speed() local
252 cr0 = readw(ps->base + SSP_CR0); in pl022_spi_set_speed()
253 writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0); in pl022_spi_set_speed()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | rmr_switch.S | 42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
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| /u-boot/arch/m68k/include/asm/coldfire/ |
| A D | pwm.h | 15 u8 cr0; member
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| /u-boot/include/ |
| A D | ppc_asm.tmpl | 193 * Note: code which follows this uses cr0.eq (set if from kernel),
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