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Searched refs:cs (Results 1 – 25 of 492) sorted by relevance

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/u-boot/board/freescale/corenet_ds/
A Dp4080ds_ddr.c78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
111 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
112 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
142 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
143 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
144 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
[all …]
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c108 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
230 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
432 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
531 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
620 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
680 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
723 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
838 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
915 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
956 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_read_leveling.c92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
122 cs, pup); in ddr3_read_leveling_hw()
129 (u32) cs, 1); in ddr3_read_leveling_hw()
203 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
620 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
623 cs)); in ddr3_read_leveling_single_cs_rl_mode()
730 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
1025 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1028 cs)); in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_spd.c896 for (cs = 0; cs < MAX_CS; cs++) {
920 for (cs = 0; cs < MAX_CS; cs++) {
936 for (cs = 0; cs < MAX_CS; cs++) {
1013 for (cs = 0; cs < MAX_CS; cs++) {
1036 for (cs = 0; cs < MAX_CS; cs++) {
1047 for (cs = 0; cs < MAX_CS; cs++) {
1062 for (cs = 0; cs < MAX_CS; cs++) {
1074 for (cs = 0; cs < MAX_CS; cs++) {
1111 for (cs = 0; cs < MAX_CS; cs++) {
1122 for (cs = 0; cs < MAX_CS; cs++) {
[all …]
A Dddr3_dfs.c118 u32 cs = 0; in ddr3_dfs_high_2_low() local
196 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
442 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
468 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
499 u32 cs = 0; in ddr3_dfs_high_2_low()
676 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
774 u32 cs = 0; in ddr3_dfs_low_2_high() local
1005 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1137 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1163 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
[all …]
A Dddr3_dqs.c133 u32 cs, ecc, reg; in ddr3_dqs_centralization_rx() local
151 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
154 (u32) cs, 1); in ddr3_dqs_centralization_rx()
215 u32 cs, ecc, reg; in ddr3_dqs_centralization_tx() local
233 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()
236 (u32) cs, 1); in ddr3_dqs_centralization_tx()
1089 cs, in ddr3_special_pattern_i_search()
1240 cs, in ddr3_special_pattern_ii_search()
1275 cs, 1); in ddr3_set_dqs_centralization_results()
1278 cs, 1); in ddr3_set_dqs_centralization_results()
[all …]
/u-boot/arch/arm/mach-omap2/omap3/
A Dsdrc.c75 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
89 if (!cs) in get_sdr_cs_offset()
107 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
110 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
111 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
112 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
113 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
114 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
115 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
121 if (!mem_ok(cs)) in write_sdrc_timings()
[all …]
A Dspl_id_nand.c38 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
39 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
40 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) in identify_nand_chip()
46 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
49 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); in identify_nand_chip()
52 *mfr = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
53 *id = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_regs.h118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) argument
121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) argument
124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) argument
231 #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8) argument
236 #define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8) argument
268 #define CS_EXIST_OFFS(cs) (CS_EXIST_BASE + (cs)) argument
389 #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) argument
401 #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) argument
404 #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) argument
[all …]
/u-boot/board/tqc/tqm834x/
A Dtqm834x.c77 int cs; in dram_init() local
84 for(cs = 0; cs < 4; ++cs) { in dram_init()
85 set_cs_bounds(cs, in dram_init()
89 set_cs_config(cs, INITIAL_CS_CONFIG); in dram_init()
106 for(cs = 0; cs < 4; ++cs) { in dram_init()
107 debug("\nDetecting Bank%d\n", cs); in dram_init()
109 bank_size = get_ddr_bank_size(cs, in dram_init()
304 set_cs_config(cs, 0); in get_ddr_bank_size()
327 im->ddr.csbnds[cs].csbnds = 0x00000000; in set_cs_bounds()
329 im->ddr.csbnds[cs].csbnds = in set_cs_bounds()
[all …]
/u-boot/drivers/spi/
A Dmt7620_spi.c103 writel(cfg, &ms->m[cs]->cfg); in mt7620_spi_master_setup()
105 writel(SPI_HIGH, &ms->m[cs]->ctl); in mt7620_spi_master_setup()
111 mt7620_spi_master_setup(ms, cs); in mt7620_spi_set_cs()
159 ret = mt7620_spi_busy_poll(ms, cs); in mt7620_spi_read()
177 writel(*buf++, &ms->m[cs]->data); in mt7620_spi_write()
180 ret = mt7620_spi_busy_poll(ms, cs); in mt7620_spi_write()
196 int cs, ret = 0; in mt7620_spi_xfer() local
207 cs = spi_chip_select(dev); in mt7620_spi_xfer()
208 if (cs < 0 || cs >= MT7620_SPI_NUM_CS) { in mt7620_spi_xfer()
214 mt7620_spi_set_cs(ms, cs, true); in mt7620_spi_xfer()
[all …]
A Dfsl_espi.c29 unsigned int cs; member
88 com |= ESPI_COM_CS(cs); in fsl_spi_cs_activate()
311 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in espi_claim_bus()
317 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
322 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
325 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
329 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
333 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
386 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
462 espi_claim_bus(fsl, fsl->cs); in fsl_espi_claim_bus()
[all …]
/u-boot/drivers/video/
A Dhitachi_tx18d42vm_lcd.c20 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
25 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
34 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
50 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
52 cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
56 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
61 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
70 lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); in hitachi_tx18d42vm_init()
74 lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */ in hitachi_tx18d42vm_init()
79 gpio_free(cs); in hitachi_tx18d42vm_init()
/u-boot/drivers/memory/
A Dstm32-fmc2-ebi.c178 int cs) in stm32_fmc2_ebi_check_mux() argument
190 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
203 int cs) in stm32_fmc2_ebi_check_sync_trans() argument
215 int cs) in stm32_fmc2_ebi_check_async_trans() argument
227 int cs) in stm32_fmc2_ebi_check_cpsize() argument
240 int cs) in stm32_fmc2_ebi_check_address_hold() argument
257 int cs) in stm32_fmc2_ebi_check_clk_period() argument
270 int cs) in stm32_fmc2_ebi_check_cclk() argument
272 if (cs) in stm32_fmc2_ebi_check_cclk()
861 int cs) in stm32_fmc2_ebi_parse_prop() argument
[all …]
A Dti-aemif.c15 #define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ argument
16 + (cs * 4))
37 static void aemif_configure(int cs, struct aemif_config *cfg) in aemif_configure() argument
43 tmp |= (1 << cs); in aemif_configure()
48 tmp |= (1 << cs); in aemif_configure()
52 tmp = __raw_readl(AEMIF_CONFIG(cs)); in aemif_configure()
65 __raw_writel(tmp, AEMIF_CONFIG(cs)); in aemif_configure()
70 int cs; in aemif_init() local
77 for (cs = 0; cs < num_cs; cs++) in aemif_init()
78 aemif_configure(cs, config + cs); in aemif_init()
/u-boot/board/freescale/ls1043ardb/
A Dddr.h49 .cs[0].bnds = 0x0000007F,
50 .cs[1].bnds = 0,
51 .cs[2].bnds = 0,
52 .cs[3].bnds = 0,
53 .cs[0].config = 0x80040322,
54 .cs[0].config_2 = 0,
55 .cs[1].config = 0,
56 .cs[1].config_2 = 0,
57 .cs[2].config = 0,
58 .cs[3].config = 0,
/u-boot/arch/arm/mach-omap2/
A Dmem-common.c42 u32 mem_ok(u32 cs) in mem_ok() argument
47 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); in mem_ok()
66 writel(0, &cs->config7); in enable_gpmc_cs_config()
69 writel(gpmc_config[0], &cs->config1); in enable_gpmc_cs_config()
70 writel(gpmc_config[1], &cs->config2); in enable_gpmc_cs_config()
71 writel(gpmc_config[2], &cs->config3); in enable_gpmc_cs_config()
72 writel(gpmc_config[3], &cs->config4); in enable_gpmc_cs_config()
73 writel(gpmc_config[4], &cs->config5); in enable_gpmc_cs_config()
74 writel(gpmc_config[5], &cs->config6); in enable_gpmc_cs_config()
77 (1 << 6)), &cs->config7); in enable_gpmc_cs_config()
[all …]
/u-boot/test/dm/
A Dspi.c35 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
44 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
62 sandbox_sf_unbind_emul(state_get_current(), busnum, cs); in dm_test_spi_find()
63 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
67 ut_assertok(sandbox_sf_bind_emul(state, busnum, cs, bus, node, in dm_test_spi_find()
69 ut_assertok(spi_find_bus_and_cs(busnum, cs, &bus, &dev)); in dm_test_spi_find()
70 ut_assertok(spi_get_bus_and_cs(busnum, cs, speed, mode, in dm_test_spi_find()
73 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
88 sandbox_sf_unbind_emul(state_get_current(), busnum, cs); in dm_test_spi_find()
181 const int busnum = 0, cs = 0, mode = 0; in dm_test_spi_xfer() local
[all …]
/u-boot/board/kontron/sl28/
A Dddr.c22 .cs[0].bnds = 0x0000007f,
23 .cs[0].config = 0x80044402,
24 .cs[1].bnds = 0x008000ff,
25 .cs[1].config = 0x80004402,
67 ddr_cfg_regs.cs[1].bnds = 0; in fsl_initdram()
68 ddr_cfg_regs.cs[1].config = 0; in fsl_initdram()
69 ddr_cfg_regs.cs[1].config_2 = 0; in fsl_initdram()
/u-boot/board/atmel/at91sam9261ek/
A Dat91sam9261ek.c53 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
56 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
58 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
62 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
65 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
67 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
101 &smc->cs[2].setup); in at91sam9261ek_dm9000_hw_init()
104 &smc->cs[2].pulse); in at91sam9261ek_dm9000_hw_init()
106 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
115 &smc->cs[2].setup); in at91sam9261ek_dm9000_hw_init()
[all …]
/u-boot/include/
A Dspi.h75 unsigned int cs; member
147 unsigned int cs;
173 unsigned int cs);
186 #define spi_alloc_slave(_struct, bus, cs) \ argument
188 sizeof(_struct), bus, cs)
199 #define spi_alloc_slave_base(bus, cs) \ argument
200 spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
218 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
323 int spi_cs_is_valid(unsigned int bus, unsigned int cs);
566 int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
[all …]
/u-boot/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen1.c30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
A Dmpc85xx_ddr_gen3.c85 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
86 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
89 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
97 csn, csn_bnds_backup, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
109 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
454 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
457 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
458 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
459 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
[all …]
/u-boot/cmd/
A Dspi.c29 static unsigned int cs; variable
36 static int do_spi_xfer(int bus, int cs) in do_spi_xfer() argument
45 snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); in do_spi_xfer()
49 ret = spi_get_bus_and_cs(bus, cs, freq, mode, "spi_generic_drv", in do_spi_xfer()
54 slave = spi_setup_slave(bus, cs, freq, mode); in do_spi_xfer()
56 printf("Invalid device %d:%d\n", bus, cs); in do_spi_xfer()
119 cs = simple_strtoul(cp+1, &cp, 10); in do_spi()
121 cs = bus; in do_spi()
156 if (do_spi_xfer(bus, cs)) in do_spi()
/u-boot/board/ronetix/pm9261/
A Dpm9261.c50 &smc->cs[3].setup); in pm9261_nand_hw_init()
54 &smc->cs[3].pulse); in pm9261_nand_hw_init()
57 &smc->cs[3].cycle); in pm9261_nand_hw_init()
67 &smc->cs[3].mode); in pm9261_nand_hw_init()
92 &smc->cs[2].setup); in pm9261_dm9000_hw_init()
96 &smc->cs[2].pulse); in pm9261_dm9000_hw_init()
99 &smc->cs[2].cycle); in pm9261_dm9000_hw_init()
105 &smc->cs[2].mode); in pm9261_dm9000_hw_init()

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