Searched refs:cs_enable_reg_val (Results 1 – 3 of 3) sorted by relevance
| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_centralization.c | 73 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization() local
85 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
484 cs_enable_reg_val[if_id], in ddr3_tip_centralization()
506 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_special_rx() local
522 cs_enable_reg_val, in ddr3_tip_special_rx()
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| A D | ddr3_training_leveling.c | 44 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling() local
66 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
295 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
407 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */ in ddr3_tip_dynamic_per_bit_read_leveling() local
440 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
747 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
808 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_write_leveling() local
841 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
1141 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
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| A D | ddr3_training_pbs.c | 51 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_pbs() local
64 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
871 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()
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