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Searched refs:ctl (Results 1 – 25 of 103) sorted by relevance

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/u-boot/cmd/
A Duniverse.c148 ctl = 0x00000000; in universe_pci_slave_window()
151 ctl = 0x00010000; in universe_pci_slave_window()
154 ctl = 0x00020000; in universe_pci_slave_window()
160 ctl |= 0x00000000; in universe_pci_slave_window()
163 ctl |= 0x00008000; in universe_pci_slave_window()
168 ctl |= 0x00001000; in universe_pci_slave_window()
198 writel(ctl, &dev->uregs->lsi[i].ctl); in universe_pci_slave_window()
245 ctl = 0x00000000; in universe_vme_slave_window()
248 ctl = 0x00010000; in universe_vme_slave_window()
251 ctl = 0x00020000; in universe_vme_slave_window()
[all …]
A Dtsi148.c167 ctl = 0x00000000; in tsi148_pci_slave_window()
170 ctl = 0x00000001; in tsi148_pci_slave_window()
173 ctl = 0x00000002; in tsi148_pci_slave_window()
179 ctl |= 0x00000000; in tsi148_pci_slave_window()
225 ctl = 0x00000000; in tsi148_eval_vam()
228 ctl = 0x00000010; in tsi148_eval_vam()
231 ctl = 0x00000020; in tsi148_eval_vam()
251 return ctl; in tsi148_eval_vam()
318 unsigned int ctl; in tsi148_vme_gcsr_window() local
342 unsigned int ctl; in tsi148_vme_crcsr_window() local
[all …]
/u-boot/arch/arm/mach-imx/
A Dmmdc_size.c18 u32 ctl; member
27 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
28 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
29 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
30 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
42 unsigned int ctl = readl(&mem->ctl); in imx_ddr_size() local
46 bits += ESD_MMDC_CTL_GET_ROW(ctl); in imx_ddr_size()
47 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; in imx_ddr_size()
49 bits += ESD_MMDC_CTL_GET_WIDTH(ctl); in imx_ddr_size()
50 bits += ESD_MMDC_CTL_GET_CS1(ctl); in imx_ddr_size()
/u-boot/board/synopsys/hsdk/
A Dclk-lib.c17 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) in soc_clk_ctl() argument
35 if (ctl & CLK_ON) { in soc_clk_ctl()
41 if ((ctl & CLK_SET) && rate) { in soc_clk_ctl()
42 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; in soc_clk_ctl()
48 if (ctl & CLK_OFF) { in soc_clk_ctl()
62 if (ctl & CLK_MHZ) in soc_clk_ctl()
65 if ((ctl & CLK_GET) && rate) in soc_clk_ctl()
68 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ)) in soc_clk_ctl()
70 else if (ctl & CLK_PRINT) in soc_clk_ctl()
/u-boot/drivers/ram/sifive/
A Dfu540_ddr.c89 struct fu540_ddrctl *ctl; member
125 writel(0x0, DENALI_CTL_209 + ctl); in fu540_ddr_setup_range_protection()
127 writel(0x0, DENALI_CTL_212 + ctl); in fu540_ddr_setup_range_protection()
128 writel(0x0, DENALI_CTL_214 + ctl); in fu540_ddr_setup_range_protection()
129 writel(0x0, DENALI_CTL_216 + ctl); in fu540_ddr_setup_range_protection()
130 setbits_le32(DENALI_CTL_224 + ctl, in fu540_ddr_setup_range_protection()
132 writel(0xFFFFFFFF, DENALI_CTL_225 + ctl); in fu540_ddr_setup_range_protection()
134 setbits_le32(DENALI_CTL_208 + ctl, in fu540_ddr_setup_range_protection()
143 setbits_le32(DENALI_CTL_0 + ctl, 0x1); in fu540_ddr_start()
226 u32 reg = readl(DENALI_CTL_0 + ctl); in fu540_ddr_get_dram_class()
[all …]
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_tuning.c92 reg = readl(&ctl->addrmap1); in get_nb_bank()
117 reg = readl(&ctl->addrmap2); in get_nb_col()
135 reg = readl(&ctl->addrmap3); in get_nb_col()
153 reg = readl(&ctl->addrmap4); in get_nb_col()
172 reg = readl(&ctl->addrmap5); in get_nb_row()
192 reg = readl(&ctl->addrmap6); in get_nb_row()
310 u8 nb_row = get_nb_row(ctl); in config_BIST()
311 u8 nb_col = get_nb_col(ctl); in config_BIST()
540 config_BIST(ctl, phy); in bit_deskew()
953 config_BIST(ctl, phy); in eye_training()
[all …]
A Dstm32mp1_ddr.c303 return (u32)priv->ctl; in get_base_addr()
601 ret = readl_poll_timeout(&ctl->swstat, swstat, in wait_sw_done_ack()
644 start_sw_done(ctl); in stm32mp1_refresh_disable()
650 wait_sw_done_ack(ctl); in stm32mp1_refresh_disable()
656 start_sw_done(ctl); in stm32mp1_refresh_restore()
664 wait_sw_done_ack(ctl); in stm32mp1_refresh_restore()
751 (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
758 clrsetbits_le32(&priv->ctl->init0, in stm32mp1_ddr_init()
802 start_sw_done(priv->ctl); in stm32mp1_ddr_init()
804 wait_sw_done_ack(priv->ctl); in stm32mp1_ddr_init()
[all …]
A Dstm32mp1_tests.c347 static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl, in databuswalk0() argument
388 static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl, in databuswalk1() argument
428 static enum test_result test_databus(struct stm32mp1_ddrctl *ctl, in test_databus() argument
518 static enum test_result test_sso(struct stm32mp1_ddrctl *ctl, in test_sso() argument
589 static enum test_result test_random(struct stm32mp1_ddrctl *ctl, in test_random() argument
686 static enum test_result test_noise(struct stm32mp1_ddrctl *ctl, in test_noise() argument
940 switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { in test_freq_pattern()
1256 static enum test_result test_read(struct stm32mp1_ddrctl *ctl, in test_read() argument
1306 static enum test_result test_write(struct stm32mp1_ddrctl *ctl, in test_write() argument
1351 static enum test_result test_all(struct stm32mp1_ddrctl *ctl, in test_all() argument
[all …]
/u-boot/drivers/net/phy/
A Det1011c.c29 int ctl = 0; in et1011c_config() local
30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
31 if (ctl < 0) in et1011c_config()
32 return ctl; in et1011c_config()
33 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
A Dphy.c137 ctl |= BMCR_SPEED1000; in genphy_setup_forced()
139 ctl |= BMCR_SPEED100; in genphy_setup_forced()
142 ctl |= BMCR_FULLDPLX; in genphy_setup_forced()
155 int ctl; in genphy_restart_aneg() local
159 if (ctl < 0) in genphy_restart_aneg()
160 return ctl; in genphy_restart_aneg()
167 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
169 return ctl; in genphy_restart_aneg()
199 if (ctl < 0) in genphy_config_aneg()
200 return ctl; in genphy_config_aneg()
[all …]
/u-boot/arch/arm/dts/
A Dk3-am654-ddr.dtsi12 reg-names = "ss", "ctl", "phy";
24 ti,ctl-reg = <
46 ti,ctl-crc = <
52 ti,ctl-ecc = <
56 ti,ctl-map = <
75 ti,ctl-pwr = <
79 ti,ctl-timing = <
158 ti,phy-ctl = <
A Dstm32mp15-ddr.dtsi17 st,ctl-reg = <
45 st,ctl-timing = <
60 st,ctl-map = <
72 st,ctl-perf = <
/u-boot/drivers/video/nexell/
A Ds5pxx18_dp_mipi.c115 unsigned int pms, ctl; in mipi_get_phy_pll() local
124 ctl = BANDCTL_960MHZ; in mipi_get_phy_pll()
128 ctl = BANDCTL_900MHZ; in mipi_get_phy_pll()
132 ctl = BANDCTL_840MHZ; in mipi_get_phy_pll()
136 ctl = BANDCTL_750MHZ; in mipi_get_phy_pll()
140 ctl = BANDCTL_660MHZ; in mipi_get_phy_pll()
144 ctl = BANDCTL_600MHZ; in mipi_get_phy_pll()
148 ctl = BANDCTL_540MHZ; in mipi_get_phy_pll()
152 ctl = BANDCTL_512MHZ; in mipi_get_phy_pll()
192 ctl = BANDCTL_80MHZ; in mipi_get_phy_pll()
[all …]
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dtimer.h20 u32 ctl; member
28 u32 ctl; /* 0x80 */ member
36 u32 ctl; /* 0xa0 */ member
43 u32 ctl; /* 0x100 */ member
A Dwatchdog.h24 u32 ctl; /* 0x00 */ member
38 u32 ctl; /* 0x10 */ member
/u-boot/drivers/pinctrl/
A Dpinctrl_stm32.c266 const struct stm32_gpio_ctl *ctl) in stm32_gpio_config() argument
274 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || in stm32_gpio_config()
275 ctl->pupd > 2 || ctl->speed > 3) in stm32_gpio_config()
287 ctl->af << index); in stm32_gpio_config()
291 ctl->mode << index); in stm32_gpio_config()
293 ctl->speed << index); in stm32_gpio_config()
294 clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index); in stm32_gpio_config()
297 clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index); in stm32_gpio_config()
/u-boot/drivers/net/
A Dat91_emac.c94 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_EnableMDIO()
100 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_DisableMDIO()
352 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); in at91emac_init()
374 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, in at91emac_init()
375 &emac->ctl); in at91emac_init()
389 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), in at91emac_halt()
390 &emac->ctl); in at91emac_halt()
444 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); in at91emac_recv()
445 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); in at91emac_recv()
/u-boot/arch/mips/mach-ath79/ar934x/
A Dddr.c45 u32 reg, cycle, ctl; in ar934x_ddr_init() local
58 ctl = BIT(6); /* Undocumented bit :-( */ in ar934x_ddr_init()
65 ctl = 0; in ar934x_ddr_init()
78 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); in ar934x_ddr_init()
/u-boot/lib/rsa/
A Drsa-keyprop.c57 static uint32_t NOT(uint32_t ctl) in NOT() argument
59 return ctl ^ 1; in NOT()
65 static uint32_t MUX(uint32_t ctl, uint32_t x, uint32_t y) in MUX() argument
67 return y ^ (-ctl & (x ^ y)); in MUX()
350 a[u] = MUX(ctl, naw, aw); in br_i32_add()
383 a[u] = MUX(ctl, naw, aw); in br_i32_sub()
409 uint32_t w, ctl, hi2, lo2; in br_divrem() local
413 ctl = GE(w, d) | (hi >> k); in br_divrem()
416 hi = MUX(ctl, hi2, hi); in br_divrem()
417 lo = MUX(ctl, lo2, lo); in br_divrem()
[all …]
/u-boot/drivers/spi/
A Dmt7620_spi.c49 u32 ctl; member
105 writel(SPI_HIGH, &ms->m[cs]->ctl); in mt7620_spi_master_setup()
117 clrbits_32(&ms->m[cs]->ctl, SPI_HIGH); in mt7620_spi_set_cs()
119 setbits_32(&ms->m[cs]->ctl, SPI_HIGH); in mt7620_spi_set_cs()
157 setbits_32(&ms->m[cs]->ctl, START_RD); in mt7620_spi_read()
178 setbits_32(&ms->m[cs]->ctl, START_WR); in mt7620_spi_write()
/u-boot/drivers/reset/
A Dsandbox-reset-test.c16 struct reset_ctl ctl; member
27 sbrt->ctlp = &sbrt->ctl; in sandbox_reset_test_get()
28 return reset_get_by_name(dev, "test", &sbrt->ctl); in sandbox_reset_test_get()
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32mp1-ddr.txt25 - st,ctl-reg : controleur values depending of the DDR type
54 - st,ctl-timing : controleur values depending of frequency and timing parameter
70 - st,ctl-map : controleur values depending of address mapping
82 - st,ctl-perf : controleur values depending of performance and scheduling
181 st,ctl-reg = <
209 st,ctl-timing = <
224 st,ctl-map = <
236 st,ctl-perf = <
/u-boot/arch/arm/mach-keystone/
A Dclock.c54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
112 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); in configure_main_pll()
116 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); in configure_main_pll()
152 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); in configure_main_pll()
154 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); in configure_main_pll()
159 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); in configure_main_pll()
288 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { in pll_freq_get()
/u-boot/arch/arm/include/asm/arch-mx25/
A Dmacro.h84 .macro init_m3if ctl=0x00000001
86 write32 IMX_M3IF_CTRL_BASE, \ctl
/u-boot/drivers/clk/altera/
A Dclk-agilex.c510 u32 ctl; in clk_get_emac_clk_hz() local
517 ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); in clk_get_emac_clk_hz()
519 ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & in clk_get_emac_clk_hz()
522 ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & in clk_get_emac_clk_hz()
525 ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & in clk_get_emac_clk_hz()
530 if (ctl) { in clk_get_emac_clk_hz()

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