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Searched refs:ctrl (Results 1 – 25 of 366) sorted by relevance

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/u-boot/drivers/mtd/nand/raw/brcmnand/
A Dbrcmnand.c624 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh() local
709 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled() local
740 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k() local
1172 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
2417 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2498 soc->ctrl = ctrl; in brcmnand_probe()
2551 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2563 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2647 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
2673 host->ctrl = ctrl; in brcmnand_probe()
[all …]
/u-boot/arch/arm/mach-omap2/omap5/
A Dhwinit.c99 (*ctrl)->control_emif1_sdram_config_ext); in io_settings_ddr3()
102 (*ctrl)->control_emif2_sdram_config_ext); in io_settings_ddr3()
109 (*ctrl)->control_port_emif1_sdram_config); in io_settings_ddr3()
114 (*ctrl)->control_port_emif2_sdram_config); in io_settings_ddr3()
117 (*ctrl)->control_ddr_control_ext_0); in io_settings_ddr3()
493 value = readl((*ctrl)->control_pbias); in vmmc_pbias_config()
495 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
498 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
502 value = readl((*ctrl)->control_pbias); in vmmc_pbias_config()
504 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
[all …]
A Ddra7xx_iodelay.c23 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
25 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
37 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
40 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
184 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
192 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
208 if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK) in __recalibrate_iodelay_end()
212 writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_end()
294 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in late_recalibrate_iodelay()
298 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in late_recalibrate_iodelay()
[all …]
/u-boot/drivers/usb/host/
A Dxhci-mem.c108 if (!ctrl->scratchpad) in xhci_scratchpad_free()
113 free(xhci_bus_to_virt(ctrl, le64_to_cpu(ctrl->scratchpad->sp_array[0]))); in xhci_scratchpad_free()
115 free(ctrl->scratchpad); in xhci_scratchpad_free()
182 free(ctrl->dcbaa); in xhci_cleanup()
528 val_64 = xhci_virt_to_bus(ctrl, ctrl->dcbaa); in xhci_mem_init()
533 ctrl->cmd_ring = xhci_ring_alloc(ctrl, 1, true); in xhci_mem_init()
536 trb_64 = xhci_virt_to_bus(ctrl, ctrl->cmd_ring->first_seg->trbs); in xhci_mem_init()
554 ctrl->ir_set = &ctrl->run_regs->ir_set[0]; in xhci_mem_init()
557 ctrl->event_ring = xhci_ring_alloc(ctrl, ERST_NUM_SEGS, false); in xhci_mem_init()
576 deq = xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue); in xhci_mem_init()
[all …]
A Dxhci-ring.c41 if (ring == ctrl->event_ring) in last_trb()
62 if (ring == ctrl->event_ring) in last_trb_on_last_seg()
280 BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING)); in xhci_queue_command()
298 queue_trb(ctrl, ctrl->cmd_ring, false, fields); in xhci_queue_command()
339 if (ctrl->hci_version < 0x100 && !(ctrl->quirks & XHCI_MTK_HOST)) in xhci_td_remainder()
348 if ((ctrl->quirks & XHCI_MTK_HOST) && (ctrl->hci_version < 0x100)) in xhci_td_remainder()
403 inc_deq(ctrl, ctrl->event_ring); in xhci_acknowledge_event()
407 xhci_virt_to_bus(ctrl, ctrl->event_ring->dequeue) | ERST_EHB); in xhci_acknowledge_event()
450 if (!event_ready(ctrl)) in xhci_wait_for_event()
507 xhci_acknowledge_event(ctrl); in abort_td()
[all …]
A Dehci-hcd.c199 ctrl->ops.set_usb_mode(ctrl); in ehci_reset()
726 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); in ehci_submit_root()
821 switch (ctrl->ops.get_port_speed(ctrl, reg)) { in ehci_submit_root()
887 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg); in ehci_submit_root()
997 ctrl->ops = *ops; in ehci_setup_ops()
1153 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); in usb_lowlevel_init()
1156 if (!ctrl->hccr || !ctrl->hcor) in usb_lowlevel_init()
1166 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); in usb_lowlevel_init()
1696 ctrl->priv = ctrl; in ehci_register()
1707 ret = ctrl->ops.init_after_reset(ctrl); in ehci_register()
[all …]
A Dxhci.c202 ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset); in xhci_reset_hw()
828 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, in xhci_check_maxpacket()
1240 hccr = ctrl->hccr; in xhci_lowlevel_init()
1241 hcor = ctrl->hcor; in xhci_lowlevel_init()
1352 ctrl->hccr = hccr; in usb_lowlevel_init()
1353 ctrl->hcor = hcor; in usb_lowlevel_init()
1378 if (ctrl->hcor) { in usb_lowlevel_stop()
1535 ctrl->dev = dev; in xhci_register()
1553 ctrl->hccr = hccr; in xhci_register()
1554 ctrl->hcor = hcor; in xhci_register()
[all …]
/u-boot/drivers/ddr/microchip/
A Dddr2.c116 struct ddr2_ctrl_regs *ctrl; in ddr2_ctrl_init() local
118 ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); in ddr2_ctrl_init()
125 ddr_set_arbiter(ctrl, arb_params); in ddr2_ctrl_init()
141 &ctrl->refcfg); in ddr2_ctrl_init()
147 &ctrl->pwrcfg); in ddr2_ctrl_init()
191 &ctrl->dlycfg3); in ddr2_ctrl_init()
194 writel(0x0, &ctrl->odtcfg); in ddr2_ctrl_init()
195 writel(BIT(16), &ctrl->odtencfg); in ddr2_ctrl_init()
197 &ctrl->odtcfg); in ddr2_ctrl_init()
202 &ctrl->xfercfg); in ddr2_ctrl_init()
[all …]
/u-boot/arch/arm/mach-omap2/omap4/
A Dhwinit.c54 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); in do_io_settings()
55 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); in do_io_settings()
58 (*ctrl)->control_lpddr2io1_2); in do_io_settings()
66 (*ctrl)->control_lpddr2io2_2); in do_io_settings()
78 (*ctrl)->control_ldosram_iva_voltage_ctrl); in do_io_settings()
81 (*ctrl)->control_ldosram_mpu_voltage_ctrl); in do_io_settings()
92 if (!readl((*ctrl)->control_efuse_1)) in do_io_settings()
181 value = readl((*ctrl)->control_pbiaslite); in vmmc_pbias_config()
183 writel(value, (*ctrl)->control_pbiaslite); in vmmc_pbias_config()
184 value = readl((*ctrl)->control_pbiaslite); in vmmc_pbias_config()
[all …]
/u-boot/drivers/mtd/nand/raw/
A Dfsl_elbc_nand.c160 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in set_addr() local
200 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_run_command() local
251 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_do_read() local
285 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_cmdfunc() local
437 if (ctrl->oob || ctrl->column != 0 || in fsl_elbc_cmdfunc()
495 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_write_buf() local
519 in_8(&ctrl->addr[ctrl->index] + len - 1); in fsl_elbc_write_buf()
532 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_read_byte() local
535 if (ctrl->index < ctrl->read_bytes) in fsl_elbc_read_byte()
549 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_read_buf() local
[all …]
A Dfsl_ifc_nand.c227 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in set_addr() local
261 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_run_command() local
336 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_do_read() local
374 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_cmdfunc() local
529 ctrl->index - ctrl->column); in fsl_ifc_cmdfunc()
580 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_write_buf() local
608 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_read_byte() local
615 if (ctrl->index < ctrl->read_bytes) { in fsl_ifc_read_byte()
632 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_read_byte16() local
639 if (ctrl->index < ctrl->read_bytes) { in fsl_ifc_read_byte16()
[all …]
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip-core.c26 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
46 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() local
69 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_mux_route() local
156 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_pinctrl_get_gpio_mux() local
200 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_mux() local
251 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_drive_perpin() local
297 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_pull() local
312 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_schmitt() local
394 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
592 return ctrl;
[all …]
/u-boot/drivers/pwm/
A Drk_pwm.c63 u32 ctrl; in rk_pwm_set_config() local
67 ctrl = readl(priv->base + regs->ctrl); in rk_pwm_set_config()
73 ctrl |= PWM_LOCK; in rk_pwm_set_config()
74 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config()
97 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config()
108 u32 ctrl; in rk_pwm_set_enable() local
112 ctrl = readl(priv->base + regs->ctrl); in rk_pwm_set_enable()
120 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_enable()
166 .ctrl = 0x0c,
180 .ctrl = 0x0c,
[all …]
/u-boot/drivers/video/nexell/
A Ds5pxx18_dp.c78 swap_rb = ctrl->swap_RB; in dp_control_setup()
79 yc_order = ctrl->yc_order; in dp_control_setup()
81 vclk_invert = ctrl->clk_inv_lv0 | ctrl->clk_inv_lv1; in dp_control_setup()
86 rgb_pvd = ctrl->d_rgb_pvd; in dp_control_setup()
92 de_cp2 = ctrl->d_de_cp2; in dp_control_setup()
96 ctrl->ev_start_offset != 0 || ctrl->ev_end_offset != 0) { in dp_control_setup()
98 v_veo = ctrl->vs_end_offset; in dp_control_setup()
100 e_veo = ctrl->ev_end_offset; in dp_control_setup()
130 6 : ctrl->clk_src_lv0); in dp_control_setup()
175 ctrl->clk_src_lv0, ctrl->clk_div_lv0, ctrl->clk_inv_lv0, in dp_control_setup()
[all …]
/u-boot/drivers/video/
A Dnexell_display.c93 ctrl->vs_start_offset = in nx_display_parse_dp_ctrl()
111 ctrl->clk_src_lv0, ctrl->clk_div_lv0, in nx_display_parse_dp_ctrl()
112 ctrl->clk_src_lv1, ctrl->clk_div_lv1); in nx_display_parse_dp_ctrl()
114 ctrl->out_format, ctrl->invert_field, in nx_display_parse_dp_ctrl()
115 ctrl->swap_RB, ctrl->yc_order); in nx_display_parse_dp_ctrl()
117 ctrl->delay_mask, ctrl->d_rgb_pvd, in nx_display_parse_dp_ctrl()
118 ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2); in nx_display_parse_dp_ctrl()
120 ctrl->vs_start_offset, ctrl->vs_end_offset, in nx_display_parse_dp_ctrl()
121 ctrl->ev_start_offset, ctrl->ev_end_offset); in nx_display_parse_dp_ctrl()
123 ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0, in nx_display_parse_dp_ctrl()
[all …]
/u-boot/drivers/sound/
A Dtegra_i2s.c31 clrsetbits_le32(&regs->ctrl, I2S_CTRL_XFER_EN_TX, in tegra_i2s_transmit_enable()
39 u32 ctrl = readl(&regs->ctrl); in i2s_tx_init() local
42 ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK); in i2s_tx_init()
43 ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK; in i2s_tx_init()
44 ctrl |= I2S_CTRL_LRCK_L_LOW; in i2s_tx_init()
47 ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX); in i2s_tx_init()
50 ctrl |= I2S_CTRL_MASTER_ENABLE; in i2s_tx_init()
53 ctrl &= ~I2S_CTRL_BIT_SIZE_MASK; in i2s_tx_init()
54 ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT; in i2s_tx_init()
55 writel(ctrl, &regs->ctrl); in i2s_tx_init()
/u-boot/arch/arm/mach-orion5x/
A Dcpu.c97 writel(0, &winregs[0].ctrl); in orion5x_config_adr_windows()
103 ORION5X_WIN_ENABLE), &winregs[0].ctrl); in orion5x_config_adr_windows()
105 writel(0, &winregs[1].ctrl); in orion5x_config_adr_windows()
111 ORION5X_WIN_ENABLE), &winregs[1].ctrl); in orion5x_config_adr_windows()
113 writel(0, &winregs[2].ctrl); in orion5x_config_adr_windows()
119 writel(0, &winregs[3].ctrl); in orion5x_config_adr_windows()
125 writel(0, &winregs[4].ctrl); in orion5x_config_adr_windows()
131 writel(0, &winregs[5].ctrl); in orion5x_config_adr_windows()
137 writel(0, &winregs[6].ctrl); in orion5x_config_adr_windows()
143 writel(0, &winregs[7].ctrl); in orion5x_config_adr_windows()
[all …]
/u-boot/arch/arm/cpu/arm926ejs/mx25/
A Dtimer.c37 writel(GPT_CTRL_SWR, &gpt->ctrl); in timer_init()
42 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
45 writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, in timer_init()
46 &gpt->ctrl); in timer_init()
47 writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); in timer_init()
/u-boot/arch/arm/cpu/arm1136/mx35/
A Dtimer.c33 writel(GPTCR_SWR, &gpt->ctrl); in timer_init()
38 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
41 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
42 &gpt->ctrl); in timer_init()
43 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); in timer_init()
/u-boot/arch/arc/lib/
A Dcache.c281 unsigned int ctrl; in __slc_enable() local
284 ctrl &= ~SLC_CTRL_DIS; in __slc_enable()
290 unsigned int ctrl; in __slc_disable() local
293 ctrl |= SLC_CTRL_DIS; in __slc_disable()
377 unsigned int ctrl; in __slc_entire_op() local
387 ctrl |= SLC_CTRL_IM; in __slc_entire_op()
425 unsigned int ctrl; in __slc_rgn_op() local
443 ctrl |= SLC_CTRL_IM; in __slc_rgn_op()
448 ctrl &= ~SLC_CTRL_RGN_OP_INV; in __slc_rgn_op()
689 unsigned int ctrl; in __before_dc_op() local
[all …]
/u-boot/arch/arm/mach-kirkwood/
A Dcache.c14 u32 ctrl; in l2_cache_disable() local
16 ctrl = readfr_extra_feature_reg(); in l2_cache_disable()
17 ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN; in l2_cache_disable()
18 writefr_extra_feature_reg(ctrl); in l2_cache_disable()
/u-boot/arch/arm/mach-lpc32xx/
A Ddevices.c17 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; variable
26 clrbits_le32(&ctrl->loop, in lpc32xx_uart_init()
36 clrsetbits_le32(&ctrl->clkmode, in lpc32xx_uart_init()
113 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); in lpc32xx_usb_init()
119 uint32_t ctrl = readl(&clk->i2cclk_ctrl); in lpc32xx_i2c_init() local
121 ctrl |= CLK_I2C1_ENABLE; in lpc32xx_i2c_init()
123 ctrl |= CLK_I2C2_ENABLE; in lpc32xx_i2c_init()
124 writel(ctrl, &clk->i2cclk_ctrl); in lpc32xx_i2c_init()
/u-boot/drivers/fpga/
A Dsocfpga_gen5.c22 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()
42 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
57 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
73 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
76 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()
79 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
94 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
112 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_init()
146 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
194 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/u-boot/board/xes/common/
A Dactl_nand.c16 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) in nand_addr_hwcontrol() argument
21 if (ctrl & NAND_CTRL_CHANGE) { in nand_addr_hwcontrol()
27 if (ctrl & NAND_CLE) in nand_addr_hwcontrol()
29 if (ctrl & NAND_ALE) in nand_addr_hwcontrol()
31 if (ctrl & NAND_NCE) in nand_addr_hwcontrol()
/u-boot/drivers/net/
A Dftmac110.c286 uint64_t ctrl; in ftmac110_send() local
299 ctrl = le64_to_cpu(txd->ctrl); in ftmac110_send()
311 ctrl &= FTMAC110_TXD_CLRMASK; in ftmac110_send()
315 ctrl |= FTMAC110_TXD_OWNER; in ftmac110_send()
317 txd->ctrl = cpu_to_le64(ctrl); in ftmac110_send()
332 uint64_t ctrl; in ftmac110_recv() local
340 ctrl = le64_to_cpu(rxd->ctrl); in ftmac110_recv()
341 if (ctrl & FTMAC110_RXD_OWNER) in ftmac110_recv()
356 ctrl &= FTMAC110_RXD_CLRMASK; in ftmac110_recv()
357 ctrl |= FTMAC110_RXD_OWNER; in ftmac110_recv()
[all …]

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