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Searched refs:ctrl_core_sma_sw_0 (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap5/
A Ddra7xx_iodelay.c37 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
40 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
208 if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK) in __recalibrate_iodelay_end()
A Dprcm-regs.c385 .ctrl_core_sma_sw_0 = 0x4A0023FC,
1021 (*ctrl)->ctrl_core_sma_sw_0; in clrset_spare_register()
/u-boot/arch/arm/include/asm/
A Domap_common.h484 u32 ctrl_core_sma_sw_0; member

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