Home
last modified time | relevance | path

Searched refs:ctrl_lpddr2ch (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap5/
A Dhw_data.c663 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
671 .ctrl_lpddr2ch = 0x0,
682 .ctrl_lpddr2ch = 0x0,
693 .ctrl_lpddr2ch = 0x40404040,
705 .ctrl_lpddr2ch = 0x40404040,
717 .ctrl_lpddr2ch = 0x40404040,
A Dhwinit.c65 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_lpddr2()
66 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_lpddr2()
92 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_ddr3()
96 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_ddr3()
/u-boot/arch/arm/include/asm/arch-omap5/
A Domap.h246 u32 ctrl_lpddr2ch; member

Completed in 12 milliseconds