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Searched refs:cwl (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_topology.c26 unsigned int cwl; in mv_ddr_cwl_calc() local
29 cwl = 9; in mv_ddr_cwl_calc()
31 cwl = 10; in mv_ddr_cwl_calc()
33 cwl = 11; in mv_ddr_cwl_calc()
35 cwl = 12; in mv_ddr_cwl_calc()
37 cwl = 14; in mv_ddr_cwl_calc()
39 cwl = 16; in mv_ddr_cwl_calc()
41 cwl = 0; in mv_ddr_cwl_calc()
43 return cwl; in mv_ddr_cwl_calc()
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_spd.c576 u32 reg, tmp, cwl; local
1089 cwl = 5; /* CWL = 5 */
1091 cwl = 6; /* CWL = 6 */
1093 cwl = 7; /* CWL = 7 */
1095 cwl = 8; /* CWL = 8 */
1097 cwl = 9; /* CWL = 9 */
1099 cwl = 10; /* CWL = 10 */
1101 cwl = 11; /* CWL = 11 */
1103 cwl = 12; /* CWL = 12 */
1105 cwl = 12; /* CWL = 12 */
[all …]
A Dddr3_dfs.c999 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1185 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1497 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
A Dddr3_hw_training.h268 u32 cwl; member
A Dddr3_hw_training.c147 dram_info.cwl = reg; in ddr3_hw_training()
/u-boot/arch/arm/mach-keystone/
A Dddr3_spd.c123 u32 cwl; member
254 spd->cwl = 0; in ddrtimingcalculation()
256 spd->cwl = 1; in ddrtimingcalculation()
258 spd->cwl = 2; in ddrtimingcalculation()
260 spd->cwl = 3; in ddrtimingcalculation()
262 spd->cwl = 4; in ddrtimingcalculation()
264 spd->cwl = 5; in ddrtimingcalculation()
357 (spd->cwl & 7) << 3 | (spd->pasr & 7); in init_ddr3param()
371 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | in init_ddr3param()
/u-boot/drivers/ddr/fsl/
A Dctrl_regs.c91 cwl = 9; in compute_cas_write_latency()
93 cwl = 10; in compute_cas_write_latency()
95 cwl = 11; in compute_cas_write_latency()
97 cwl = 12; in compute_cas_write_latency()
99 cwl = 14; in compute_cas_write_latency()
101 cwl = 16; in compute_cas_write_latency()
126 cwl = 5; in compute_cas_write_latency()
128 cwl = 6; in compute_cas_write_latency()
130 cwl = 7; in compute_cas_write_latency()
132 cwl = 8; in compute_cas_write_latency()
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/u-boot/drivers/ram/octeon/
A Docteon3_lmc.c3163 mp0.s.cwl = 0; in lmc_modereg_params0()
3165 mp0.s.cwl = 1; in lmc_modereg_params0()
3167 mp0.s.cwl = 2; in lmc_modereg_params0()
3169 mp0.s.cwl = 3; in lmc_modereg_params0()
3171 mp0.s.cwl = 4; in lmc_modereg_params0()
3173 mp0.s.cwl = 5; in lmc_modereg_params0()
3175 mp0.s.cwl = 6; in lmc_modereg_params0()
3177 mp0.s.cwl = 7; in lmc_modereg_params0()
3186 mp0.s.cwl + 9 in lmc_modereg_params0()
3187 + ((mp0.s.cwl > 2) ? (mp0.s.cwl - 3) * 2 : 0), mp0.s.cwl); in lmc_modereg_params0()
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/u-boot/arch/x86/cpu/quark/
A Dsmc.c262 uint8_t cwl; in ddrphy_init() local
267 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()
430 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
/u-boot/arch/mips/mach-octeon/include/mach/cvmx/
A Dcvmx-lmcx-defs.h2341 uint64_t cwl:3; member
2359 uint64_t cwl:3; member

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