| /u-boot/cmd/ |
| A D | time.c | 9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
30 ulong cycles = 0; in do_time() local
37 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
38 report_time(cycles); in do_time()
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| /u-boot/drivers/ram/k3-j721e/ |
| A D | lpddr4.c | 1222 *cycles = in readpdwakeup()
1228 *cycles = in readpdwakeup()
1235 *cycles = in readpdwakeup()
1249 *cycles = in readsrshortwakeup()
1255 *cycles = in readsrshortwakeup()
1262 *cycles = in readsrshortwakeup()
1276 *cycles = in readsrlongwakeup()
1282 *cycles = in readsrlongwakeup()
1289 *cycles = in readsrlongwakeup()
1303 *cycles = in readsrlonggatewakeup()
[all …]
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| A D | lpddr4_obj_if.h | 260 …pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
271 …nst lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
353 … (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
363 …refreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
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| A D | lpddr4_if.h | 466 …pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
477 …nst lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
557 …dr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
567 …trefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
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| A D | lpddr4_sanity.h | 50 …nst lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
57 …tyfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
851 …onst lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles) in lpddr4_sanityfunction23() argument
864 else if (cycles == NULL) in lpddr4_sanityfunction23()
1129 …ityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles) in lpddr4_sanityfunction32() argument
1138 else if (cycles == NULL) in lpddr4_sanityfunction32()
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| /u-boot/arch/xtensa/lib/ |
| A D | time.c | 26 static void delay_cycles(unsigned cycles) in delay_cycles() argument
29 unsigned expiry = get_ccount() + cycles; in delay_cycles()
41 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
43 fake_ccount += cycles; in delay_cycles()
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| /u-boot/board/keymile/km_arm/ |
| A D | kwbimage_256M8_1.cfg | 118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
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| A D | kwbimage-memphis.cfg | 65 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
133 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
134 # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
136 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
141 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
143 # bit15-12: 1000, internal ODT de-assertion x cycles after write
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| A D | kwbimage_128M16_1.cfg | 118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
197 # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
198 # (ODT turn off delay 2,5 clk cycles)
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
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| /u-boot/board/buffalo/lsxl/ |
| A D | kwbimage-lsxhl.cfg | 38 # bit4: 1, T2 mode, addr/cmd are driven for two cycles
139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| A D | kwbimage-lschl.cfg | 139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| /u-boot/board/d-link/dns325/ |
| A D | kwbimage.cfg | 128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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| /u-boot/arch/powerpc/cpu/mpc83xx/initreg/ |
| A D | Kconfig.lcrr | 24 prompt "Additional delay cycles for SDRAM control signals"
68 prompt "External address delay cycles"
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| /u-boot/board/tbs/tbs2910/ |
| A D | tbs2910.cfg | 96 /* interleaved bank access (row/bank/col), 5 cycles additional read delay */
109 /* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
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| /u-boot/arch/powerpc/cpu/mpc83xx/elbc/ |
| A D | Kconfig.elbc1 | 324 bool "2 cycles"
328 bool "4 cycles"
332 bool "8 cycles"
505 bool "4 idle clock cycles inserted"
509 bool "8 idle clock cycles inserted"
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| A D | Kconfig.elbc4 | 324 bool "2 cycles"
328 bool "4 cycles"
332 bool "8 cycles"
505 bool "4 idle clock cycles inserted"
509 bool "8 idle clock cycles inserted"
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| A D | Kconfig.elbc0 | 324 bool "2 cycles"
328 bool "4 cycles"
332 bool "8 cycles"
505 bool "4 idle clock cycles inserted"
509 bool "8 idle clock cycles inserted"
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| A D | Kconfig.elbc2 | 324 bool "2 cycles"
328 bool "4 cycles"
332 bool "8 cycles"
505 bool "4 idle clock cycles inserted"
509 bool "8 idle clock cycles inserted"
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| A D | Kconfig.elbc3 | 324 bool "2 cycles"
328 bool "4 cycles"
332 bool "8 cycles"
505 bool "4 idle clock cycles inserted"
509 bool "8 idle clock cycles inserted"
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| /u-boot/doc/ |
| A D | README.bootcount | 22 cycles.
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| /u-boot/drivers/clk/at91/ |
| A D | clk-main.c | 234 unsigned int cycles = 16; in clk_main_probe_frequency() local
238 while (cycles--) { in clk_main_probe_frequency()
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| /u-boot/board/freescale/mx6memcal/ |
| A D | Kconfig | 185 Enter a latency in number of cycles. This will be added to
195 Enter a latency in number of cycles. This will be added to
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 25 …f the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self…
26 …ed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic powe…
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| /u-boot/drivers/bootcount/ |
| A D | Kconfig | 133 int "Maximum number of reboot cycles allowed"
136 Set the Maximum number of reboot cycles allowed without the boot
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| /u-boot/arch/arm/dts/ |
| A D | omap36xx.dtsi | 55 ti,clock-cycles = <8>;
|