Searched refs:davinci_emif_regs (Results 1 – 5 of 5) sorted by relevance
184 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()187 __raw_writel(val, &davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()592 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()596 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()600 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()604 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()608 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()612 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()616 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()620 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()[all …]
31 struct davinci_emif_regs { struct74 #define davinci_emif_regs \ argument75 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
281 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); in arch_cpu_init()284 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); in arch_cpu_init()
209 &davinci_emif_regs->ab2cr); /* CS3 */ in board_init()
329 &davinci_emif_regs->ab2cr); /* CS3 */ in board_init()
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