| /u-boot/drivers/rtc/ |
| A D | imxdi.c | 31 u32 dcr; /* Control Reg */ member
168 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
169 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
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| /u-boot/drivers/spi/ |
| A D | stm32_qspi.c | 29 u32 dcr; /* 0x04 */ member
120 u32 dcr; member
398 setbits_le32(&priv->regs->dcr, in stm32_qspi_probe()
421 writel(flash->dcr, &priv->regs->dcr); in stm32_qspi_claim_bus()
429 flash->dcr = readl(&priv->regs->dcr); in stm32_qspi_claim_bus()
478 clrsetbits_le32(&priv->regs->dcr, in stm32_qspi_set_speed()
499 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
501 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
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| /u-boot/drivers/mmc/ |
| A D | ftsdc010_mci.c | 198 uint32_t dcr; in ftsdc010_request() local
203 dcr = 0; in ftsdc010_request()
205 dcr |= FTSDC010_DCR_FIFO_RST; in ftsdc010_request()
207 writel(dcr, ®s->dcr); in ftsdc010_request()
220 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; in ftsdc010_request()
222 dcr |= FTSDC010_DCR_DATA_WRITE; in ftsdc010_request()
223 writel(dcr, ®s->dcr); in ftsdc010_request()
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| /u-boot/board/sysam/amcore/ |
| A D | amcore.c | 84 out_be16(&dc->dcr, 0x8200 | RC); in dram_init()
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| /u-boot/board/freescale/m5235evb/ |
| A D | m5235evb.c | 58 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
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| /u-boot/arch/nds32/lib/ |
| A D | asm-offsets.c | 61 OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ in main()
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| /u-boot/drivers/timer/ |
| A D | stm32_timer.c | 48 u32 dcr; member
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| /u-boot/arch/m68k/include/asm/ |
| A D | immap_5307.h | 100 u16 dcr; member
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| A D | immap_5235.h | 91 u16 dcr; /* 0x00 Control register */ member
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| A D | immap_5275.h | 110 u32 dcr; member
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| /u-boot/include/faraday/ |
| A D | ftsdc010.h | 24 unsigned int dcr; /* 0x1c - data control reg */ member
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a23.c | 104 writel(0x40b, &mctl_phy->dcr); in mctl_init()
106 writel(0x1000040b, &mctl_phy->dcr); in mctl_init()
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| A D | dram_sun4i.c | 155 if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) == in mctl_get_number_of_lanes()
620 writel(reg_val, &dram->dcr); in dramc_init_helper()
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| /u-boot/arch/m68k/include/asm/coldfire/ |
| A D | lcd.h | 26 u32 dcr; /* 0x30 DMA Control Register */ member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun4i.h | 16 u32 dcr; /* 0x04 dram configuration register */ member
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| A D | dram_sun9i.h | 109 u32 dcr; /* 0x88 DRAM configuration register */ member
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| A D | dram_sun50i_h6.h | 186 u32 dcr; /* 0x100 */ member
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| A D | dram_sun8i_a23.h | 180 u32 dcr; /* 0x44 */ member
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| A D | dram_sun6i.h | 173 u32 dcr; /* 0x30 */ member
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| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ddr.h | 121 u32 dcr; member
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| A D | stm32mp1_ddr_regs.h | 154 u32 dcr; /* 0x30 DRAM Configuration*/ member
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| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk3288.c | 330 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
346 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
586 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
589 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
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| A D | sdram_rk3188.c | 287 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
528 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
531 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | ddr_rk3288.h | 177 u32 dcr; member
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| /u-boot/include/synopsys/ |
| A D | dwcddr21mctl.h | 16 unsigned int dcr; /* DRAM Configuration */ member
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