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Searched refs:ddr (Results 1 – 25 of 247) sorted by relevance

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/u-boot/drivers/ddr/fsl/
A Dfsl_ddr_gen4.c57 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
124 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
126 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
147 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
157 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
229 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
235 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
272 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
283 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen3.c30 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
163 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
219 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
233 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
244 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
253 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
264 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
420 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
506 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
[all …]
A Darm_ddr_gen3.c36 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
43 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
47 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
52 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
57 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
69 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
145 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc86xx_ddr.c20 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
24 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
27 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
44 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
48 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
64 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
55 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
78 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen1.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
76 struct ccsr_ddr __iomem *ddr = in ddr_enable_ecc() local
[all …]
A Dctrl_regs.c227 ddr->cs[i].config = (0 in set_csn_config()
440 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
493 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
621 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
714 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
850 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
1939 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1969 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1987 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
2216 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
[all …]
A Dutil.c31 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
36 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
40 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
45 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
50 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
179 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
195 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
202 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
347 struct ccsr_ddr __iomem *ddr; in fsl_ddr_sync_memctl_refresh() local
352 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_sync_memctl_refresh()
[all …]
/u-boot/board/sbc8641d/
A Dsbc8641d.c105 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
106 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; in fixed_sdram()
107 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
108 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; in fixed_sdram()
117 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; in fixed_sdram()
118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; in fixed_sdram()
119 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; in fixed_sdram()
130 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; in fixed_sdram()
134 ddr = &immap->im_ddr2; in fixed_sdram()
148 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; in fixed_sdram()
[all …]
/u-boot/post/cpu/mpc83xx/
A Decc.c29 __raw_writel(0, &ddr->capture_address); in ecc_clear()
30 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
31 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
32 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
33 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
53 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
82 ecc_clear(ddr); in ecc_post_test()
122 ddr->data_err_inject_hi, in ecc_post_test()
123 ddr->data_err_inject_lo, in ecc_post_test()
129 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_post_test()
[all …]
/u-boot/arch/powerpc/cpu/mpc83xx/
A Decc.c19 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
21 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
47 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
78 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_print_status()
103 struct ccsr_ddr __iomem *ddr = &immap->ddr; in do_ecc() local
105 ddr83xx_t *ddr = &immap->ddr; in do_ecc() local
134 ddr->capture_ecc = 0; in do_ecc()
151 ddr->err_sbe = val; in do_ecc()
164 ddr->err_sbe = val; in do_ecc()
199 val = ddr->err_detect; in do_ecc()
[all …]
A Dspd_sdram.c35 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
134 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
242 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
267 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
475 ddr->timing_cfg_0 = (0 in spd_sdram()
538 ddr->timing_cfg_1 = in spd_sdram()
630 ddr->timing_cfg_2 = (0 in spd_sdram()
693 ddr->sdram_mode = in spd_sdram()
711 ddr->sdram_mode2 = 0; in spd_sdram()
761 ddr->sdram_cfg2 = (0 in spd_sdram()
[all …]
/u-boot/board/sbc8548/
A Dddr.c92 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
95 out_be32(&ddr->cs0_bnds, 0x0000007f); in fixed_sdram()
96 out_be32(&ddr->cs1_bnds, 0x008000ff); in fixed_sdram()
97 out_be32(&ddr->cs2_bnds, 0x00000000); in fixed_sdram()
98 out_be32(&ddr->cs3_bnds, 0x00000000); in fixed_sdram()
100 out_be32(&ddr->cs0_config, 0x80010101); in fixed_sdram()
101 out_be32(&ddr->cs1_config, 0x80010101); in fixed_sdram()
102 out_be32(&ddr->cs2_config, 0x00000000); in fixed_sdram()
103 out_be32(&ddr->cs3_config, 0x00000000); in fixed_sdram()
110 out_be32(&ddr->sdram_cfg, 0x4300C000); in fixed_sdram()
[all …]
/u-boot/board/freescale/ls1021atsn/
A Dls1021atsn.c34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
48 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
51 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
54 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
60 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
63 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
73 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
81 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot/board/freescale/ls1021aiot/
A Dls1021aiot.c56 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
58 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
59 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
68 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); in ddrmc_init()
69 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
71 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
81 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
84 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
89 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot/board/socrates/
A Dsdram.c28 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
34 ddr->cs0_config = 0; in fixed_sdram()
35 ddr->sdram_cfg = 0; in fixed_sdram()
37 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
38 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
39 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
41 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
42 ddr->sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
44 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; in fixed_sdram()
[all …]
/u-boot/board/gdsys/mpc8308/
A Dsdram.c45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
54 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
55 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
58 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
/u-boot/board/mpc8308_p1m/
A Dsdram.c38 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
42 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
46 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
47 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
50 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
51 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
52 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
53 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8308rdb/
A Dsdram.c42 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
46 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
51 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
54 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
55 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
56 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
57 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8315erdb/
A Dsdram.c60 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
64 im->ddr.cs_config[1] = 0; in fixed_sdram()
67 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
69 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
70 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
75 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
77 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
78 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
79 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8349emds/
A Dmpc8349emds.c108 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
112 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
114 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
115 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
123 im->ddr.csbnds[2].csbnds = in fixed_sdram()
130 im->ddr.cs_config[0] = 0; in fixed_sdram()
131 im->ddr.cs_config[1] = 0; in fixed_sdram()
132 im->ddr.cs_config[3] = 0; in fixed_sdram()
137 im->ddr.sdram_cfg = in fixed_sdram()
147 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8313erdb/
A Dsdram.c66 im->ddr.csbnds[0].csbnds = in fixed_sdram()
73 im->ddr.cs_config[1] = 0; in fixed_sdram()
76 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
77 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
78 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
79 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
86 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; in fixed_sdram()
88 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; in fixed_sdram()
89 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
90 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc832xemds/
A Dmpc832xemds.c137 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; in fixed_sdram()
139 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
140 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
141 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
142 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
143 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
144 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
145 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
146 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
147 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8349itx/
A Dmpc8349itx.c51 im->ddr.csbnds[0].csbnds = in fixed_sdram()
55 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
58 im->ddr.cs_config[1] = 0; in fixed_sdram()
59 im->ddr.cs_config[2] = 0; in fixed_sdram()
60 im->ddr.cs_config[3] = 0; in fixed_sdram()
68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
71 im->ddr.sdram_mode = in fixed_sdram()
73 im->ddr.sdram_interval = in fixed_sdram()
80 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; in fixed_sdram()
134 volatile ddr83xx_t *ddr = &im->ddr; in dram_init() local
[all …]
/u-boot/board/ids/ids8313/
A Dids8313.c76 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
77 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
80 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
81 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
82 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
84 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
89 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); in fixed_sdram()
90 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); in fixed_sdram()
92 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
93 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); in fixed_sdram()
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