| /u-boot/board/gardena/smart-gateway-at91sam/ |
| A D | spl.c | 80 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
82 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
84 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
90 ddr2->rtr = 0x411; in ddr2_conf()
92 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
101 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
106 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
117 struct atmel_mpddrc_config ddr2; in mem_init() local
120 ddr2_conf(&ddr2); in mem_init()
134 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /u-boot/board/atmel/sama5d3_xplained/ |
| A D | sama5d3_xplained.c | 135 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
137 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
139 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
151 ddr2->rtr = 0x411; in ddr2_conf()
153 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
162 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
167 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
176 struct atmel_mpddrc_config ddr2; in mem_init() local
178 ddr2_conf(&ddr2); in mem_init()
185 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /u-boot/board/laird/wb45n/ |
| A D | wb45n.c | 148 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
150 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
152 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
158 ddr2->rtr = 0x411; in ddr2_conf()
160 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
169 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
174 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
184 struct atmel_mpddrc_config ddr2; in mem_init() local
187 ddr2_conf(&ddr2); in mem_init()
198 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /u-boot/board/laird/wb50n/ |
| A D | wb50n.c | 142 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
144 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
146 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | in ddr2_conf()
153 ddr2->rtr = 0x411; in ddr2_conf()
155 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
164 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
169 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
178 struct atmel_mpddrc_config ddr2; in mem_init() local
180 ddr2_conf(&ddr2); in mem_init()
189 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /u-boot/board/atmel/at91sam9x5ek/ |
| A D | at91sam9x5ek.c | 154 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
156 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
158 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
164 ddr2->rtr = 0x411; in ddr2_conf()
166 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
175 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
180 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
191 struct atmel_mpddrc_config ddr2; in mem_init() local
194 ddr2_conf(&ddr2); in mem_init()
208 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /u-boot/board/atmel/sama5d4_xplained/ |
| A D | sama5d4_xplained.c | 155 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
157 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
159 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
167 ddr2->rtr = 0x2b0; in ddr2_conf()
169 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
178 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
183 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
192 struct atmel_mpddrc_config ddr2; in mem_init() local
194 ddr2_conf(&ddr2); in mem_init()
201 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /u-boot/board/atmel/sama5d4ek/ |
| A D | sama5d4ek.c | 141 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
143 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
145 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
152 ddr2->rtr = 0x2b0; in ddr2_conf()
154 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
163 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
168 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
177 struct atmel_mpddrc_config ddr2; in mem_init() local
181 ddr2_conf(&ddr2); in mem_init()
201 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /u-boot/board/siemens/corvus/ |
| A D | board.c | 139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
148 ddr2->rtr = 0x24b; in ddr2_conf()
150 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
159 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
164 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
172 struct atmel_mpddrc_config ddr2; in mem_init() local
174 ddr2_conf(&ddr2); in mem_init()
179 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
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| /u-boot/board/mini-box/picosam9g45/ |
| A D | picosam9g45.c | 52 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
54 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
56 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
61 ddr2->rtr = 0x24b; in ddr2_conf()
63 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
72 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
77 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
86 struct atmel_mpddrc_config ddr2; in mem_init() local
89 ddr2_conf(&ddr2); in mem_init()
100 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
[all …]
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| /u-boot/board/atmel/at91sam9m10g45ek/ |
| A D | at91sam9m10g45ek.c | 98 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
100 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
102 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
107 ddr2->rtr = 0x24b; in ddr2_conf()
109 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
118 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
123 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
131 struct atmel_mpddrc_config ddr2; in mem_init() local
133 ddr2_conf(&ddr2); in mem_init()
138 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
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| /u-boot/board/atmel/at91sam9n12ek/ |
| A D | at91sam9n12ek.c | 240 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
242 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
244 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
250 ddr2->rtr = 0x411; in ddr2_conf()
252 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
261 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
266 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
276 struct atmel_mpddrc_config ddr2; in mem_init() local
279 ddr2_conf(&ddr2); in mem_init()
293 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /u-boot/board/atmel/sama5d3xek/ |
| A D | sama5d3xek.c | 208 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
210 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
212 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
224 ddr2->rtr = 0x411; in ddr2_conf()
226 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
235 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
240 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
249 struct atmel_mpddrc_config ddr2; in mem_init() local
251 ddr2_conf(&ddr2); in mem_init()
258 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /u-boot/drivers/ddr/microchip/ |
| A D | Makefile | 4 obj-$(CONFIG_MACH_PIC32) += ddr2.o
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| /u-boot/arch/mips/mach-octeon/include/mach/cvmx/ |
| A D | cvmx-lmcx-defs.h | 1087 uint64_t ddr2:1; member
1107 uint64_t ddr2:1; member
|