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Searched refs:ddr2xdqsclk (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c238 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, in cm_basic_init()
294 ret = cm_write_with_phase(cfg->ddr2xdqsclk, in cm_basic_init()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h42 u32 ddr2xdqsclk; member

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