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Searched refs:ddr_ddrc_cfg (Results 1 – 12 of 12) sorted by relevance

/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c12 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1720 .ddrc_cfg = ddr_ddrc_cfg,
1721 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1722 .ddrc_cfg = ddr_ddrc_cfg,
1723 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
A Dlpddr4_timing_2gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1722 .ddrc_cfg = ddr_ddrc_cfg,
1723 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
A Dlpddr4_timing_3gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1722 .ddrc_cfg = ddr_ddrc_cfg,
1723 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
A Dlpddr4_timing_4gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1722 .ddrc_cfg = ddr_ddrc_cfg,
1723 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/beacon/imx8mn/
A Dlpddr4_2g_timing.c12 struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1429 .ddrc_cfg = ddr_ddrc_cfg,
1430 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
A Dlpddr4_timing.c9 struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1422 .ddrc_cfg = ddr_ddrc_cfg,
1423 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c11 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1835 .ddrc_cfg = ddr_ddrc_cfg,
1836 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c11 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1838 .ddrc_cfg = ddr_ddrc_cfg,
1839 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c13 struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1202 .ddrc_cfg = ddr_ddrc_cfg,
1203 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c9 struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1837 .ddrc_cfg = ddr_ddrc_cfg,
1838 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c15 struct dram_cfg_param ddr_ddrc_cfg[] = { variable
1839 .ddrc_cfg = ddr_ddrc_cfg,
1840 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),

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