Searched refs:ddr_ddrphy_trained_csr (Results 1 – 12 of 12) sorted by relevance
| /u-boot/board/google/imx8mq_phanbell/ |
| A D | lpddr4_timing_1g.c | 269 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1726 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1727 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/technexion/pico-imx8mq/ |
| A D | lpddr4_timing_1gb.c | 271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| A D | lpddr4_timing_2gb.c | 271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| A D | lpddr4_timing_3gb.c | 271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| A D | lpddr4_timing_4gb.c | 271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/beacon/imx8mn/ |
| A D | lpddr4_2g_timing.c | 276 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1435 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1436 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| A D | lpddr4_timing.c | 273 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1428 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1429 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/phytec/phycore_imx8mm/ |
| A D | lpddr4_timing.c | 325 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/phytec/phycore_imx8mp/ |
| A D | lpddr4_timing.c | 330 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1844 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1845 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/freescale/imx8mn_evk/ |
| A D | ddr4_timing.c | 267 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1208 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1209 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/freescale/imx8mp_evk/ |
| A D | lpddr4_timing.c | 329 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1843 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1844 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
| /u-boot/board/toradex/verdin-imx8mm/ |
| A D | lpddr4_timing.c | 329 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1845 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1846 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
Completed in 17 milliseconds