Home
last modified time | relevance | path

Searched refs:ddr_fsp0_2d_cfg (Results 1 – 12 of 12) sorted by relevance

/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c1071 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1713 .fsp_cfg = ddr_fsp0_2d_cfg,
1714 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1715 .fsp_cfg = ddr_fsp0_2d_cfg,
1716 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
A Dlpddr4_timing_2gb.c1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1715 .fsp_cfg = ddr_fsp0_2d_cfg,
1716 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
A Dlpddr4_timing_3gb.c1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1715 .fsp_cfg = ddr_fsp0_2d_cfg,
1716 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
A Dlpddr4_timing_4gb.c1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1715 .fsp_cfg = ddr_fsp0_2d_cfg,
1716 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/beacon/imx8mn/
A Dlpddr4_2g_timing.c792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1422 .fsp_cfg = ddr_fsp0_2d_cfg,
1423 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
A Dlpddr4_timing.c789 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1415 .fsp_cfg = ddr_fsp0_2d_cfg,
1416 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c1167 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1828 .fsp_cfg = ddr_fsp0_2d_cfg,
1829 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c1172 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1831 .fsp_cfg = ddr_fsp0_2d_cfg,
1832 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c924 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1195 .fsp_cfg = ddr_fsp0_2d_cfg,
1196 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c1171 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1830 .fsp_cfg = ddr_fsp0_2d_cfg,
1831 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c1171 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable
1832 .fsp_cfg = ddr_fsp0_2d_cfg,
1833 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),

Completed in 17 milliseconds