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Searched refs:ddr_fsp1_cfg (Results 1 – 12 of 12) sorted by relevance

/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c1031 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1706 .fsp_cfg = ddr_fsp1_cfg,
1707 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c1033 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1708 .fsp_cfg = ddr_fsp1_cfg,
1709 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
A Dlpddr4_timing_2gb.c1033 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1708 .fsp_cfg = ddr_fsp1_cfg,
1709 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
A Dlpddr4_timing_3gb.c1033 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1708 .fsp_cfg = ddr_fsp1_cfg,
1709 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
A Dlpddr4_timing_4gb.c1033 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1708 .fsp_cfg = ddr_fsp1_cfg,
1709 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/beacon/imx8mn/
A Dlpddr4_2g_timing.c716 struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1408 .fsp_cfg = ddr_fsp1_cfg,
1409 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
A Dlpddr4_timing.c713 struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1401 .fsp_cfg = ddr_fsp1_cfg,
1402 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c1087 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1814 .fsp_cfg = ddr_fsp1_cfg,
1815 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c1092 static struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1817 .fsp_cfg = ddr_fsp1_cfg,
1818 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c838 struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1181 .fsp_cfg = ddr_fsp1_cfg,
1182 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c1091 struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1816 .fsp_cfg = ddr_fsp1_cfg,
1817 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c1091 struct dram_cfg_param ddr_fsp1_cfg[] = { variable
1818 .fsp_cfg = ddr_fsp1_cfg,
1819 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),

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