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Searched refs:ddr_in32 (Results 1 – 7 of 7) sorted by relevance

/u-boot/drivers/ddr/fsl/
A Dfsl_ddr_gen4.c31 while (ddr_in32(ptr) & bits) { in set_wait_for_bits_clear()
275 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
298 temp32 = ddr_in32(&ddr->debug[25]); in fsl_ddr_set_memctl_regs()
307 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
407 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
456 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
477 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
569 cs0_bnds = ddr_in32(&ddr->cs0_bnds); in fsl_ddr_set_memctl_regs()
570 cs1_bnds = ddr_in32(&ddr->cs1_bnds); in fsl_ddr_set_memctl_regs()
596 mtcr = ddr_in32(&ddr->mtcr); in fsl_ddr_set_memctl_regs()
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A Dutil.c57 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; in fsl_ddr_get_version()
58 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; in fsl_ddr_get_version()
186 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info()
188 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
195 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
202 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
239 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); in print_ddr_info()
244 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; in print_ddr_info()
373 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()
378 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()
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A Darm_ddr_gen3.c188 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
194 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
197 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()
224 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
233 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
244 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
A Dctrl_regs.c2607 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()
2612 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()
2625 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()
2637 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()
2645 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()
A Dmpc85xx_ddr_gen3.c358 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
/u-boot/include/
A Dfsl_ddr.h23 #define ddr_in32(a) in_le32(a) macro
29 #define ddr_in32(a) in_be32(a) macro
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dsoc.c494 tmp = ddr_in32(&ddr->eor); in erratum_a008850_post()
581 tmp = ddr_in32(&ddr->ddr_cdr1); in ddr_enable_0v9_volt()

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