Searched refs:ddr_mode (Results 1 – 16 of 16) sorted by relevance
| /u-boot/drivers/ddr/marvell/axp/ |
| A D | ddr3_init.c | 780 MV_DRAM_MODES *ddr_mode; in ddr3_static_training_init() local
784 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_training_init()
787 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
789 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
790 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
792 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
880 MV_DRAM_MODES *ddr_mode; in ddr3_static_mc_init() local
884 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_mc_init()
887 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()
888 ddr_mode->regs[j].reg_value); in ddr3_static_mc_init()
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| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | spl.h | 42 enum ddr_mode mem_type; /* Type of on-board memory */
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| A D | dmc.h | 431 enum ddr_mode { enum
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| /u-boot/arch/arm/mach-exynos/ |
| A D | clock_init.h | 40 enum ddr_mode mem_type; /* Memory type */
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| A D | dmc_common.c | 75 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll()
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| A D | clock_init_exynos5.c | 484 static void clock_get_mem_selection(enum ddr_mode *mem_type, in clock_get_mem_selection()
501 enum ddr_mode mem_type; in get_arm_ratios()
525 enum ddr_mode mem_type; in clock_get_mem_timings()
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| A D | exynos5_setup.h | 945 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
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| /u-boot/drivers/mmc/ |
| A D | sdhci-cadence.c | 151 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()
156 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()
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| A D | xenon_sdhci.c | 300 if (host->mmc->ddr_mode) { in xenon_mmc_phy_set()
409 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
423 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
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| A D | tmio-common.c | 540 if (mmc->ddr_mode) in tmio_sd_set_ddr_mode()
564 if (mmc->ddr_mode && (divisor == 1)) in tmio_sd_set_clk_rate()
653 mmc->clock, mmc->ddr_mode, mmc->bus_width); in tmio_sd_set_ios()
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| A D | dw_mmc.c | 130 timeout /= mmc->ddr_mode ? 2 : 1; in dwmci_get_timeout()
492 if (mmc->ddr_mode)
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| A D | mmc.c | 191 mmc->ddr_mode = mmc_is_mode_ddr(mode); in mmc_select_mode()
317 if (mmc->ddr_mode) in mmc_set_blocklen()
2601 if (mmc->ddr_mode) { in mmc_startup()
2814 mmc->ddr_mode = 0; in mmc_get_op_cond()
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| A D | fsl_esdhc_imx.c | 493 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); in esdhc_send_cmd_common()
647 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; in set_sysctl()
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| A D | octeontx_hsmmc.c | 2324 if (a->ddr_only && !mmc->ddr_mode) { in octeontx_mmc_execute_tuning()
2462 if (mmc->ddr_mode && bus_width) in octeontx_mmc_set_ios()
2476 slot->last_clock, mmc->clock, mmc->ddr_mode); in octeontx_mmc_set_ios()
2511 !mmc->ddr_mode) { in octeontx_mmc_set_ios()
3135 mmc->ddr_mode ? "yes" : "no", in octeontx_mmc_set_output_bus_timing()
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| /u-boot/include/ |
| A D | mmc.h | 722 int ddr_mode; member
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| /u-boot/cmd/ |
| A D | mmc.c | 50 mmc->ddr_mode ? " DDR" : ""); in print_mmcinfo()
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