Searched refs:ddr_phy (Results 1 – 8 of 8) sorted by relevance
| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
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| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| A D | sdram_rk3036.c | 369 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_pctrl_reset() local
387 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
391 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
400 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_dll_bypass_set() local
415 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
424 &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
430 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
485 struct rk3036_ddr_phy *ddr_phy = priv->phy; in data_training() local
493 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, in data_training()
627 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_cfg() local
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| /u-boot/arch/arm/include/asm/arch-mx7/ |
| A D | mx7-ddr.h | 126 struct ddr_phy { struct
167 struct ddr_phy *ddr_phy_regs_val, argument
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | ddr.c | 29 struct ddr_phy *ddr_phy_regs_val, in mx7_dram_cfg()
35 struct ddr_phy *const ddr_phy_regs = in mx7_dram_cfg()
36 (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR; in mx7_dram_cfg()
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| /u-boot/board/technexion/pico-imx7d/ |
| A D | spl.c | 73 static struct ddr_phy ddr_phy_regs_val = {
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| /u-boot/board/compulab/cl-som-imx7/ |
| A D | spl.c | 67 static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
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| /u-boot/arch/riscv/dts/ |
| A D | fu540-c000-u-boot.dtsi | 76 "ddr_phy", "gemgxl_reset";
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| /u-boot/drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 202 CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, 1, div_table2, "TBG-A-S"),
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