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Searched refs:ddr_type (Results 1 – 25 of 46) sorted by relevance

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/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dddr.h10 enum ddr_type { enum
18 int board_ddr_power_init(enum ddr_type ddr_type);
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dddr.c75 static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type) in mt7628_ddr_pad_ldo_config() argument
82 if (ddr_type == DRAM_DDR1) in mt7628_ddr_pad_ldo_config()
117 if (ddr_type == DRAM_DDR1) in mt7628_ddr_pad_ldo_config()
134 int ddr_type, pkg_type, lspd; in mt7628_ddr_init() local
138 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; in mt7628_ddr_init()
146 mt7628_ddr_pad_ldo_config(ddr_type, pkg_type); in mt7628_ddr_init()
156 ddr_type = DRAM_DDR1; in mt7628_ddr_init()
158 if (ddr_type == DRAM_DDR1) { in mt7628_ddr_init()
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_init.c9 static char *ddr_type = "DDR3"; variable
37 mv_ddr_pre_training_soc_config(ddr_type); in ddr3_init()
76 printf("%s Training Sequence - FAILED\n", ddr_type); in ddr3_init()
82 mv_ddr_post_training_soc_config(ddr_type); in ddr3_init()
143 printf("%s Training Sequence - FAILED\n", ddr_type); in mv_ddr_training_params_set()
A Dmv_ddr_plat.h227 int mv_ddr_pre_training_soc_config(const char *ddr_type);
228 int mv_ddr_post_training_soc_config(const char *ddr_type);
A Dmv_ddr_plat.c1101 static int ddr3_restore_and_set_final_windows(u32 *win, const char *ddr_type) in ddr3_restore_and_set_final_windows() argument
1115 ddr_type); in ddr3_restore_and_set_final_windows()
1209 int mv_ddr_pre_training_soc_config(const char *ddr_type) in mv_ddr_pre_training_soc_config() argument
1246 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); in mv_ddr_pre_training_soc_config()
1319 int mv_ddr_post_training_soc_config(const char *ddr_type) in mv_ddr_post_training_soc_config() argument
1324 ddr3_restore_and_set_final_windows(win, ddr_type); in mv_ddr_post_training_soc_config()
/u-boot/arch/mips/mach-mtmips/mt7620/
A Ddram.c71 int ddr_type, aux; in mt7620_dram_init() local
75 ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) in mt7620_dram_init()
93 if (ddr_type == DRAM_DDR1) { in mt7620_dram_init()
100 } else if (ddr_type == DRAM_DDR2) { in mt7620_dram_init()
/u-boot/drivers/ram/octeon/
A Ddimm_spd_eeprom.c293 int ddr_type) in get_dimm_ecc() argument
295 return !!(read_spd(dimm_config, upper_dimm, BUS_WIDTH(ddr_type)) & 8); in get_dimm_ecc()
299 int ddr_type) in get_dimm_module_type() argument
327 int dimm, const char **dimm_types, int ddr_type, in report_common_dimm() argument
336 ddr_type); in report_common_dimm()
337 spd_ecc = get_dimm_ecc(dimm_config, upper_dimm, ddr_type); in report_common_dimm()
341 if_num, dimm, ddr_type, dimm_types[spd_module_type], in report_common_dimm()
398 int ddr_type; in report_dimm() local
401 ddr_type = get_ddr_type(dimm_config, upper_dimm); in report_dimm()
403 if (ddr_type == DDR4_DRAM) in report_dimm()
A Docteon_ddr.c156 int ddr_type; in octeon3_refclock() local
180 ddr_type = get_ddr_type(dimm_config, 0); in octeon3_refclock()
181 spd_dimm_type = get_dimm_module_type(dimm_config, 0, ddr_type); in octeon3_refclock()
183 debug("ddr type: 0x%x, dimm type: 0x%x\n", ddr_type, in octeon3_refclock()
186 if (ddr_type == DDR4_DRAM && in octeon3_refclock()
433 int ddr_type; in initialize_ddr_clock() local
437 ddr_type = (read_spd(&dimm_config_table[0], 0, in initialize_ddr_clock()
641 ((ddr_type == DDR4_DRAM) && in initialize_ddr_clock()
950 (ddr_type == DDR4_DRAM) ? 1 : 0; in initialize_ddr_clock()
1566 int ddr_type) in validate_ddr3_rlevel_bitmask() argument
[all …]
A Docteon3_lmc.c2660 static enum ddr_type ddr_type __section(".data");
2937 if (ddr_type == DDR4_DRAM) { in lmc_timing_params0()
3011 if (ddr_type == DDR4_DRAM) { in lmc_timing_params1()
3084 if (ddr_type == DDR4_DRAM) { in lmc_timing_params2()
3137 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3184 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3211 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3481 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params2()
3540 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params3()
6629 ddr_type); in rodt_loop()
[all …]
/u-boot/board/st/common/
A Dstpmic1.c18 int board_ddr_power_init(enum ddr_type ddr_type) in board_ddr_power_init() argument
31 switch (ddr_type) { in board_ddr_power_init()
117 switch (ddr_type) { in board_ddr_power_init()
/u-boot/drivers/ddr/imx/imx8m/
A Dddrphy_utils.c218 unsigned int i, ddr_type, tmp; in get_trained_CDD() local
223 ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; in get_trained_CDD()
224 if (ddr_type == 0x20) { in get_trained_CDD()
273 unsigned int i, ddr_type; in update_umctl2_rank_space_setting() local
277 ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; in update_umctl2_rank_space_setting()
280 if (ddr_type == 0x20) { in update_umctl2_rank_space_setting()
/u-boot/board/rockchip/evb_rk3036/
A Devb_rk3036.c15 config->ddr_type = 3; in get_ddr_config()
/u-boot/board/rockchip/kylin_rk3036/
A Dkylin_rk3036.c18 config->ddr_type = 3; in get_ddr_config()
/u-boot/board/ccv/xpress/
A Dspl.c62 .ddr_type = DDR_TYPE_DDR3,
/u-boot/board/barco/platinum/
A Dspl_picon.c138 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
A Dspl_titanium.c141 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
/u-boot/arch/x86/include/asm/arch-quark/
A Dmrc.h114 uint8_t ddr_type; /* DDR3, DDR3L */ member
/u-boot/arch/x86/include/asm/
A Dglobal_data.h24 uint16_t ddr_type; member
/u-boot/board/freescale/mx6ul_14x14_evk/
A Dmx6ul_14x14_evk.c419 .ddr_type = DDR_TYPE_LPDDR2,
459 .ddr_type = DDR_TYPE_DDR3,
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c321 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; in mpc83xx_sdram_probe() local
413 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
414 if (ddr_type > 1) { in mpc83xx_sdram_probe()
416 dev->name, ddr_type); in mpc83xx_sdram_probe()
438 ddr_type << (31 - 13) | in mpc83xx_sdram_probe()
/u-boot/arch/arm/mach-imx/mx6/
A Dlitesom.c132 .ddr_type = DDR_TYPE_DDR3,
A Dopos6ul.c132 .ddr_type = DDR_TYPE_DDR3,
/u-boot/board/engicam/common/
A Dspl.c237 .ddr_type = DDR_TYPE_DDR3,
349 .ddr_type = DDR_TYPE_DDR3,
/u-boot/board/myir/mys_6ulx/
A Dspl.c66 .ddr_type = DDR_TYPE_DDR3,
/u-boot/board/phytec/pcl063/
A Dspl.c68 .ddr_type = DDR_TYPE_DDR3,

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