Searched refs:ddr_width (Results 1 – 10 of 10) sorted by relevance
| /u-boot/drivers/ddr/marvell/axp/ |
| A D | ddr3_init.c | 361 __maybe_unused u32 ddr_width = BUS_WIDTH; in ddr3_init_main() local
487 ddr_width = 32; in ddr3_init_main()
495 ddr_width = 32; in ddr3_init_main()
497 ddr_width = 16; in ddr3_init_main()
502 status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width); in ddr3_init_main()
536 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & in ddr3_init_main()
603 status = ddr3_hw_training(target_freq, ddr_width, in ddr3_init_main()
626 status = ddr3_hw_training(target_freq, ddr_width, in ddr3_init_main()
|
| A D | ddr3_init.h | 95 int ddr3_hw_training(u32 target_freq, u32 ddr_width,
117 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
|
| A D | ddr3_sdram.c | 298 switch (dram_info->ddr_width) { in ddr3_sdram_pbs_compare()
348 if (dram_info->ddr_width > 16) { in ddr3_sdram_pbs_compare()
473 if (dram_info->ddr_width > 16) { in ddr3_sdram_direct_compare()
625 if (dram_info->ddr_width > 16) { in ddr3_sdram_dqs_compare()
|
| A D | ddr3_hw_training.c | 79 int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass, in ddr3_hw_training() argument
98 dram_info.ddr_width = ddr_width; in ddr3_hw_training()
99 dram_info.num_of_std_pups = ddr_width / PUP_SIZE; in ddr3_hw_training()
122 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena; in ddr3_hw_training()
|
| A D | ddr3_spd.c | 574 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) argument
598 status = ddr3_spd_init(&dimm_info[0], 0, *ddr_width);
627 *ddr_width);
739 if (*ddr_width == 64) {
751 if (*ddr_width == 32) {
|
| A D | ddr3_write_leveling.c | 190 u32 ddr_width, tmp_pup, idx; in ddr3_wl_supplement() local
195 ddr_width = dram_info->ddr_width; in ddr3_wl_supplement()
200 switch (ddr_width) { in ddr3_wl_supplement()
|
| A D | ddr3_pbs.c | 417 switch (dram_info->ddr_width) { in ddr3_tx_shift_dqs_adll_step_before_fail()
928 switch (dram_info->ddr_width) { in ddr3_rx_shift_dqs_to_first_fail()
1538 switch (dram_info->ddr_width) { in ddr3_load_pbs_patterns()
|
| A D | ddr3_hw_training.h | 257 u32 ddr_width; /* 32/64 Bit or 16/32 Bit */ member
|
| A D | ddr3_dqs.c | 98 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern()
|
| /u-boot/drivers/ram/octeon/ |
| A D | octeon3_lmc.c | 8735 u64 ddr_width = 4 << ((spd_org >> 0) & 0x7); in init_octeon3_ddr3_interface() local
8745 bus_width / ddr_width * in init_octeon3_ddr3_interface()
|
Completed in 31 milliseconds