Searched refs:ddr_zq_cntl (Results 1 – 16 of 16) sorted by relevance
| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 103 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
135 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
167 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
199 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
231 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
263 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
295 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
327 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
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| /u-boot/drivers/ddr/fsl/ |
| A D | mpc85xx_ddr_gen3.c | 143 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
216 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
341 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
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| A D | arm_ddr_gen3.c | 111 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
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| A D | fsl_ddr_gen4.c | 177 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
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| A D | ctrl_regs.c | 2216 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2225 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
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| A D | interactive.c | 670 CFG_REGS(ddr_zq_cntl), in print_fsl_memctl_config_regs()
761 CFG_REGS(ddr_zq_cntl), in fsl_ddr_regs_edit()
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 50 .ddr_zq_cntl = 0x89080600,
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| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 42 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
69 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 93 .ddr_zq_cntl = 0x8A090705,
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| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 107 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, in fixed_sdram()
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| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 84 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
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| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 76 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 236 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_immap.h | 54 u32 ddr_zq_cntl; /* ZQ calibration control*/ member
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| A D | fsl_ddr_sdram.h | 283 unsigned int ddr_zq_cntl; member
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 192 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
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