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Searched refs:ddrclkdr (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/varisys/cyrus/
A Dcyrus.c50 setbits_be32(&gur->ddrclkdr, 0x001B001B); in board_early_init_f()
/u-boot/board/keymile/kmp204x/
A Dkmp204x.c54 setbits_be32(&gur->ddrclkdr, 0x001f000f); in board_early_init_f()
/u-boot/board/freescale/corenet_ds/
A Dcorenet_ds.c99 setbits_be32(&gur->ddrclkdr, 0x001B001B); in board_early_init_f()
/u-boot/board/freescale/p2041rdb/
A Dp2041rdb.c71 setbits_be32(&gur->ddrclkdr, 0x000f000f); in board_early_init_f()
/u-boot/board/keymile/kmcent2/
A Dkmcent2.c57 setbits_be32(&gur->ddrclkdr, 0x40000000); in board_early_init_f()
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dimmap_ls102xa.h145 u32 ddrclkdr; member
/u-boot/arch/powerpc/include/asm/
A Dimmap_85xx.h1960 u32 ddrclkdr; /* DDR clock disable */ member

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