Home
last modified time | relevance | path

Searched refs:ddrdqclk (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c241 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, in cm_basic_init()
301 ret = cm_write_with_phase(cfg->ddrdqclk, in cm_basic_init()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h43 u32 ddrdqclk; member

Completed in 4 milliseconds